Abstract: A quantum bit (qubit) flip chip assembly may be formed when a qubit it formed on a first chip and an optically transmissive path is formed on a second chip. The two chips may be bonded. The optically transmissive path may provide optical access to the qubit on the first chip.

Abstract: A quantum bit (qubit) flip chip assembly may be formed when a qubit it formed on a first chip and an optically transmissive path is formed on a second chip. The two chips may be bonded using solder bumps. The optically transmissive path may provide optical access to the qubit on the first chip.

Abstract: A technique relates a structure. An inductive element is on a first surface. A capacitive element is on the first surface and a second surface. An interconnect structure is between the first surface and the second surface.

Abstract: A technique relates to a structure. A first surface includes an inductive element of a resonator. A second surface includes a first portion of a capacitive element of the resonator and at least one qubit. A second portion of the capacitive element of the resonator is on the first surface.

Abstract: A technique relates to a structure. A first surface includes an inductive element of a resonator. A second surface includes a first portion of a capacitive element of the resonator and at least one qubit. A second portion of the capacitive element of the resonator is on the first surface.

Abstract: A technique relates to correcting an area of overlap between two films created by sequential shadow mask evaporations. At least one process is performed of: correcting design features in an original layout to generate a corrected layout using a software tool, such that the corrected layout modifies shapes of the design features and correcting the design features in the original layout to generate the corrected layout using a lithographic tool, such that the corrected layout modifies the shapes of the design features. The modified shapes of the design features are patterned at locations on a wafer according to the corrected layout using the lithographic tool. A first film is deposited by an initial shadow mask evaporation and a second film by a subsequent shadow mask evaporation to produce corrected junctions at the locations on the wafer, such that the first and second films have an overlap.

Abstract: A technique relates a structure. An inductive element is on a first surface. A capacitive element is on the first surface and a second surface. An interconnect structure is between the first surface and the second surface.

Abstract: Techniques for a vertical transmon qubit device are provided. In one embodiment, a chip surface base device structure is provided that comprises a first superconducting material physically coupled to a crystalline substrate, wherein the crystalline substrate is physically coupled to a second superconducting material, wherein the second superconducting material is physically coupled to a second crystalline substrate. In one implementation, the chip surface base device structure also comprises a vertical Josephson junction located in a via of the crystalline substrate, the vertical Josephson junction comprising the first superconducting material, a tunnel barrier, and the second superconducting material. In one implementation, the chip surface base device structure also comprises a transmon qubit comprising the vertical Josephson junction and a capacitor formed between the first superconducting material and the second superconducting material.

Abstract: A method of forming metal lines that are aligned to underlying metal features that includes forming a neutral layer atop a hardmask layer that is overlying a dielectric layer. The neutral layer is composed of a neutral charged di-block polymer. Patterning the neutral layer, the hardmask layer and the dielectric layer to provide openings that are filled with a metal material to provide metal features. A self-assembled di-block copolymer material is deposited on a patterned surface of the neutral layer and the metal features. The self-assembled di-block copolymer material includes a first block composition with a first affinity for alignment to the metal features. The first block composition of the self-assembled di-block copolymer is converted to a metal that is self-aligned to the metal features.

Abstract: Techniques for a vertical Josephson junction superconducting device are provided. In one embodiment, a chip surface base device structure is provided that comprises a substrate comprising crystalline silicon that is coupled with a first superconducting layer, wherein the first superconducting layer is coupled with a second substrate comprising crystalline silicon. In one implementation, the chip surface base device structure also comprises a vertical Josephson junction located in an etched region of the substrate, the vertical Josephson junction comprising a first superconducting layer, a tunnel barrier layer, and a top superconducting layer.

Abstract: The present invention provides a process and structure of microfabricated air bridges for planar microwave resonator circuits. In an embodiment, the invention includes depositing a superconducting film on a surface of a base material, where the superconducting film is formed with a compressive stress, where the compressive stress is higher than a critical buckling stress of a defined structure, etching an exposed area of the superconducting film, thereby creating the at least one bridge, etching the base material, thereby forming a gap between the at least one bridge and the base material, depositing the at least one metal line on at least part of the superconducting film and at least part of the base material, where the at least one metal line runs under the bridge.

Abstract: A technique relates to a superconducting chip. Resonant units have resonant frequencies, and the resonant units are configured as superconducting resonators. Josephson junctions are in the resonant units, and one or more of the Josephson junctions have a shorted tunnel barrier.

Abstract: A method of forming metal lines that are aligned to underlying metal features that includes forming a neutral layer atop a hardmask layer that is overlying a dielectric layer. The neutral layer is composed of a neutral charged di-block polymer. Patterning the neutral layer, the hardmask layer and the dielectric layer to provide openings that are filled with a metal material to provide metal features. A self-assembled di-block copolymer material is deposited on a patterned surface of the neutral layer and the metal features. The self-assembled di-block copolymer material includes a first block composition with a first affinity for alignment to the metal features. The first block composition of the self-assembled di-block copolymer is converted to a metal that is self-aligned to the metal features.

Abstract: A technique relates to a superconducting chip. Resonant units have resonant frequencies, and the resonant units are configured as superconducting resonators. Josephson junctions are in the resonant units, and one or more of the Josephson junctions have a shorted tunnel barrier.

Abstract: A technique relates to forming a sidewall tunnel junction. A first conducting layer is formed using a first shadow mask evaporation. A second conducting layer is formed on a portion of the first conducting layer, where the second conducting layer is formed using a second shadow mask evaporation. An oxide layer is formed on the first conducting layer and the second conducting layer. A third conducting layer is formed on part of the oxide layer, such that the sidewall tunnel junction is positioned between the first conducting layer and the third conducting layer.

Abstract: A technique relates to forming a sidewall tunnel junction. A first conducting layer is formed using a first shadow mask evaporation. A second conducting layer is formed on a portion of the first conducting layer, where the second conducting layer is formed using a second shadow mask evaporation. An oxide layer is formed on the first conducting layer and the second conducting layer. A third conducting layer is formed on part of the oxide layer, such that the sidewall tunnel junction is positioned between the first conducting layer and the third conducting layer.

Abstract: A technique relates to a superconducting chip. Resonant units have resonant frequencies, and the resonant units are configured as superconducting resonators. Josephson junctions are in the resonant units, and one or more of the Josephson junctions have a shorted tunnel barrier.

Abstract: A technique relates to a superconducting chip. Resonant units each include a Josephson junction. The resonant units have resonant frequencies whose differences are based on a variation in the Josephson junction. A transmission medium is coupled to the resonant units, and the transmission medium is configured to output a sequence of the resonant frequencies as an identification of the chip.

Abstract: A technique relates to a superconducting chip. Resonant units each include a Josephson junction. The resonant units have resonant frequencies whose differences are based on a variation in the Josephson junction. A transmission medium is coupled to the resonant units, and the transmission medium is configured to output a sequence of the resonant frequencies as an identification of the chip.

Abstract: Hybrid pre-patterns were prepared for directed self-assembly of a given block copolymer capable of forming a lamellar domain pattern. The hybrid pre-patterns have top surfaces comprising independent elevated surfaces interspersed with adjacent recessed surfaces. The elevated surfaces are neutral wetting to the domains formed by self-assembly. Material below the elevated surfaces has greater etch-resistance than material below the recessed surfaces in a given etch process. Following other dimensional constraints of the hybrid pre-pattern described herein, a layer of the given block copolymer was formed on the hybrid pre-pattern. Self-assembly of the layer produced a lamellar domain pattern comprising self-aligned, unidirectional, perpendicularly oriented lamellae over the elevated surfaces, and parallel and/or perpendicularly oriented lamellae over recessed surfaces. The domain patterns displayed long range order along the major axis of the pre-pattern.