Abstract: Memory devices and systems with post-packaging master die selection, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies. Each memory die of the plurality includes a command/address decoder. The command/address decoders are configured to receive command and address signals from external contacts of the memory device. The command/address decoders are also configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other memory die of the plurality. Each memory die further includes circuitry configured to enable, or disable, or both individual command/address decoders of the plurality of memory dies. In some embodiments, the circuitry can enable a command/address decoder of a memory die of the plurality after the plurality of memory dies are packaged into a memory device.

Abstract: A memory device can be operated with a set of refresh control features. A host can access the memory device to discover the set of refresh control features. The host can command the memory device to change at least one of the set of refresh control features. The memory device can be operated with the original and/or changed set of refresh control features.

Abstract: Systems, apparatuses, and methods related to bloom filter implementation into a controller are described. A memory device is coupled to a memory controller. The memory controller is configured to implement a counting bloom filter, increment the counting bloom filter in response to a row activate command of the memory device, determine whether a value of the counting bloom filter exceeds a threshold value, and perform an action in response to the value exceeding the threshold value.

Abstract: Memory devices and systems with post-packaging master die selection, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies. Each memory die of the plurality includes a command/address decoder. The command/address decoders are configured to receive command and address signals from external contacts of the memory device. The command/address decoders are also configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other memory die of the plurality. Each memory die further includes circuitry configured to enable, or disable, or both individual command/address decoders of the plurality of memory dies. In some embodiments, the circuitry can enable a command/address decoder of a memory die of the plurality after the plurality of memory dies are packaged into a memory device.

Abstract: Systems and methods for finite time counting period counting of infinite data streams is presented. In particular example systems and methods enable counting row accesses to a memory media device over predetermined time intervals in order to deterministically detect row hammer attacks on the memory media device. Example embodiments use two identical tables that are reset at times offset in relation to each other in a ping-pong manner in order to ensure that there exists no false negative detections. The counting techniques described in this disclosure can be used in various types of row hammer mitigation techniques and can be implemented in content addressable memory or another type of memory. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be a dynamic random access memory type device.

Abstract: There are provided systems and methods that include at least one memory that has a plurality of memory cells. The cells may be disposed in rows and columns. The device can further include a controller that is communicatively coupled to the at least one memory, and the controller may be configured by its hardware topology and its instruction set and/or by a communicatively coupled processor or higher-level system or subsystem to maintain data integrity in the at least one memory and/or to prevent or mitigate malicious access patterns that may compromise the at least one memory. The controller may be configured to execute a deterministic protocol in conjunction with or sequentially to a probabilistic protocol to achieve one or more of the above-noted functions.

Abstract: There are provided systems and methods that include at least one memory that has a plurality of memory cells. The cells may be disposed in rows and columns. The device can further include a controller that is communicatively coupled to the at least one memory, and the controller may be configured by its hardware topology and its instruction set and/or by a communicatively coupled processor or higher-level system or subsystem to maintain data integrity in the at least one memory and/or to prevent or mitigate malicious access patterns that may compromise the at least one memory. The controller may be configured to execute a deterministic protocol in conjunction with or sequentially to a probabilistic protocol to achieve one or more of the above-noted functions.

Abstract: Apparatuses for characterizing system channels and associated methods and systems are disclosed. In one embodiment, a tester is coupled to an adaptor configured to plug into a CPU socket of a system platform (e.g., a motherboard). The motherboard includes a memory socket that is connected to the CPU socket through system channels. The adaptor may include a connector configured to physically and electrically engage with the CPU socket, an interface configured to receive test signals from the tester, and circuitry configured to internally route the test signals to the connector. The adaptor, if plugged into the CPU socket, can facilitate the tester to directly assess signal transfer characteristics of the system channels. Accordingly, the tester can determine optimum operating parameters for the memory device in view of the system channel characteristics.

Abstract: There are provided systems and methods that include at least one memory that has a plurality of memory cells. The cells may be disposed in rows and columns. The device can further include a controller that is communicatively coupled to the at least one memory, and the controller may be configured by its hardware topology and its instruction set and/or by a communicatively coupled processor or higher level system or subsystem to maintain data integrity in the at least one memory and/or to prevent or mitigate malicious access patterns that may compromise the at least one memory. The controller may be configured to execute a deterministic protocol in conjunction with or sequentially to a probabilistic protocol to achieve one or more of the above-noted functions.

Abstract: A system and method detect a row hammer attack on the memory media device and generates a hardware interrupt based on the detection of the row hammer attack. This row hammer interrupt is communicated to an operating system of a host computing device, which in turn performs an interrupt service routine including generating a command to perform a row hammer mitigation operation. This command is provided to the memory controller which performs the row hammer mitigation operation in response to the command such as activating victim row(s) of the memory media device or throttling data traffic to the memory media device.

Abstract: Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.

Abstract: Apparatuses, systems, and methods for multi-bit error detection. A memory device may store data bits and parity bits in a memory array. An error correction code (ECC) circuit may generate syndrome bits based on the data and parity bits and use the syndrome bits to correct up to a single bit error in the data and parity bits. A multi-bit error (MBE) detection circuit may detect an MBE in the data and parity based on at least one of the syndrome bits or the parity bits. For example, the MBE detection circuit may determine if the syndrome bits have a mapped or unmapped state and/or may compare the parity bits, data bits, and an additional parity bit to determine if there is an MBE. When an MBE is detected an MBE signal is activated. In some embodiments, an MBE flag may be set based on the MBE signal being active.

Abstract: Apparatuses, systems, and methods for multi-bit error detection. A memory device may store data bits and parity bits in a memory array. An error correction code (ECC) circuit may generate syndrome bits based on the data and parity bits and use the syndrome bits to correct up to a single bit error in the data and parity bits. A multi-bit error (MBE) detection circuit may detect an MBE in the data and parity based on at least one of the syndrome bits or the parity bits. For example, the MBE detection circuit may determine if the syndrome bits have a mapped or unmapped state and/or may compare the parity bits, data bits, and an additional parity bit to determine if there is an MBE. When an MBE is detected an MBE signal is activated. In some embodiments, an MBE flag may be set based on the MBE signal being active.

Abstract: Memory devices and systems with TSV health monitor circuitry, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies, a plurality of through-silicon vias (TSVs) in electrical communication with the memory dies; and circuitry. In some embodiments, the circuitry is configured to electrically couple a pair of TSVs of the plurality of TSVs to form a passive circuit. For example, the circuitry can activate a transistor electrically positioned between TSVs of the pair of TSVs to electrically couple the pair of TSVs. In these and other embodiments, the circuitry applies a test voltage to the pair of TSVs using the passive circuit to determine whether a TSV of the pair of TSVs includes degradation.

Abstract: A memory device can be operated with a set of refresh control features. A host can access the memory device to discover the set of refresh control features. The host can command the memory device to change at least one of the set of refresh control features.

Abstract: Apparatuses for characterizing system channels and associated methods and systems are disclosed. In one embodiment, a tester is coupled to an adaptor configured to plug into a CPU socket of a system platform (e.g., a motherboard). The motherboard includes a memory socket that is connected to the CPU socket through system channels. The adaptor may include a connector configured to physically and electrically engage with the CPU socket, an interface configured to receive test signals from the tester, and circuitry configured to internally route the test signals to the connector. The adaptor, if plugged into the CPU socket, can facilitate the tester to directly assess signal transfer characteristics of the system channels. Accordingly, the tester can determine optimum operating parameters for the memory device in view of the system channel characteristics.

Abstract: Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.

Abstract: Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.

Abstract: Methods, systems, and devices for phase charge sharing are described. In some memory systems or memory devices, one or more decoders may be used to bias access lines of a memory die. The decoders may transfer voltage or current between a first conductive line of the decoder and a second conductive line of the decoder via a shorting device. Transferring the voltage or current may be performed as part of or in association with an operation (e.g., an activate or pre-charge operation) to access one or more memory cells of the memory die. In some examples, the decoders may transfer voltage or current between a first conductive line of a decoder associated with a first refresh activity and a second conductive line of the decoder associated with a second refresh activity via a shorting device.

Abstract: Memory devices and systems with TSV health monitor circuitry, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies, a plurality of through-silicon vias (TSVs) in electrical communication with the memory dies; and circuitry. In some embodiments, the circuitry is configured to electrically couple a pair of TSVs of the plurality of TSVs to form a passive circuit. For example, the circuitry can activate a transistor electrically positioned between TSVs of the pair of TSVs to electrically couple the pair of TSVs. In these and other embodiments, the circuitry applies a test voltage to the pair of TSVs using the passive circuit to determine whether a TSV of the pair of TSVs includes degradation.