Patents by Inventor Markus H. Geiger

Markus H. Geiger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210173773
    Abstract: Memory devices and systems with post-packaging master die selection, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies. Each memory die of the plurality includes a command/address decoder. The command/address decoders are configured to receive command and address signals from external contacts of the memory device. The command/address decoders are also configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other memory die of the plurality. Each memory die further includes circuitry configured to enable, or disable, or both individual command/address decoders of the plurality of memory dies. In some embodiments, the circuitry can enable a command/address decoder of a memory die of the plurality after the plurality of memory dies are packaged into a memory device.
    Type: Application
    Filed: December 6, 2019
    Publication date: June 10, 2021
    Inventors: Evan C. Pearson, John H. Gentry, Michael J. Scott, Greg S. Gatlin, Lael H. Matthews, Anthony M. Geidl, Michael Roth, Markus H. Geiger, Dale H. Hiscock
  • Publication number: 20210174859
    Abstract: Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.
    Type: Application
    Filed: December 6, 2019
    Publication date: June 10, 2021
    Inventors: John H. Gentry, Michael J. Scott, Greg S. Gatlin, Lael H. Matthews, Anthony M. Geidl, Michael Roth, Markus H. Geiger, Dale H. Hiscock, Evan C. Pearson
  • Publication number: 20200342931
    Abstract: Methods, systems, and devices for phase charge sharing are described. In some memory systems or memory devices, one or more decoders may be used to bias access lines of a memory die. The decoders may transfer voltage or current between a first conductive line of the decoder and a second conductive line of the decoder via a shorting device. Transferring the voltage or current may be performed as part of or in association with an operation (e.g., an activate or pre-charge operation) to access one or more memory cells of the memory die. In some examples, the decoders may transfer voltage or current between a first conductive line of a decoder associated with a first refresh activity and a second conductive line of the decoder associated with a second refresh activity via a shorting device.
    Type: Application
    Filed: July 10, 2020
    Publication date: October 29, 2020
    Inventors: James R. Rehmeyer, George B. Raad, Debra M. Bell, Markus H. Geiger, Anthony D. Veches
  • Patent number: 10748600
    Abstract: Methods, systems, and devices for phase charge sharing are described. In some memory systems or memory devices, one or more decoders may be used to bias access lines of a memory die. The decoders may transfer voltage or current between a first conductive line of the decoder and a second conductive line of the decoder via a shorting device. Transferring the voltage or current may be performed as part of or in association with an operation (e.g., an activate or pre-charge operation) to access one or more memory cells of the memory die. In some examples, the decoders may transfer voltage or current between a first conductive line of a decoder associated with a first refresh activity and a second conductive line of the decoder associated with a second refresh activity via a shorting device.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: August 18, 2020
    Assignee: Micron Technologies, Inc.
    Inventors: James S. Rehmeyer, George B. Raad, Debra M. Bell, Markus H. Geiger, Anthony D. Veches
  • Publication number: 20200185024
    Abstract: Methods, systems, and devices for phase charge sharing are described. In some memory systems or memory devices, one or more decoders may be used to bias access lines of a memory die. The decoders may transfer voltage or current between a first conductive line of the decoder and a second conductive line of the decoder via a shorting device. Transferring the voltage or current may be performed as part of or in association with an operation (e.g., an activate or pre-charge operation) to access one or more memory cells of the memory die. In some examples, the decoders may transfer voltage or current between a first conductive line of a decoder associated with a first refresh activity and a second conductive line of the decoder associated with a second refresh activity via a shorting device.
    Type: Application
    Filed: December 11, 2018
    Publication date: June 11, 2020
    Inventors: James S. Rehmeyer, George B. Raad, Debra M. Bell, Markus H. Geiger, Anthony D. Veches