Patents by Inventor Markus Kuhn

Markus Kuhn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160049513
    Abstract: Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.
    Type: Application
    Filed: October 13, 2015
    Publication date: February 18, 2016
    Inventors: Jack T. Kavalieros, Nancy Zelick, Been-Yih Jin, Markus Kuhn, Stephen M. Cea
  • Patent number: 9159835
    Abstract: Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: October 13, 2015
    Assignee: Intel Corporation
    Inventors: Jack T. Kavalieros, Nancy Zelick, Been-Yih Jin, Markus Kuhn, Stephen M. Cea
  • Patent number: 8992582
    Abstract: A plate system for bone fixation including intermaxillary fixation which has at least one plate with one opening and at least one bone screw for securing the plate to an adjacent bone and/or other anatomical structures (e.g., the gingival) with space maintained in between. The plate system provides a fixed connection at both the plate and the bone. A method for achieving fixation while maintaining space between the plate and bone includes placement of a spacer over the desired bone screw insertion point, followed by placement of the plate over the spacer so that the bone screw may be inserted through the plate while the spacer is held in position.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: March 31, 2015
    Assignee: Stryker Leibinger GmbH & Co. KG
    Inventors: Christian Knoepfle, Manfred Schmuck, Karl Greiner, Markus Kuhn
  • Publication number: 20140249585
    Abstract: The invention relates to a surgical retaining instrument for bone plates. The retaining instrument comprises a carrying element and two plate retaining jaws arranged on the carrying element. The mutual distance of the plate retaining jaws can be changed in order to pick up or release a bone plate. Furthermore, an actuating device is provided, which has two arms, which can be moved relative to each other and which are designed to change the mutual distance of the plate retaining jaws. The carrying element is rotatably mounted relative to the arms.
    Type: Application
    Filed: January 12, 2012
    Publication date: September 4, 2014
    Applicant: STRYKER LEIBINGER GMBH & CO. KG
    Inventors: Christian Knoepfle, Karl Greiner, Manfred Schmuck, Uwe Koerner, Markus Kuhn
  • Publication number: 20140070273
    Abstract: A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.
    Type: Application
    Filed: September 5, 2013
    Publication date: March 13, 2014
    Inventors: Stephen M. Cea, Roza Kotlyar, Jack T. Kavalieros, Martin D. Giles, Tahir Ghani, Kelin J. Kuhn, Markus Kuhn, Nancy M. Zelick
  • Patent number: 8558279
    Abstract: A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: October 15, 2013
    Assignee: Intel Corporation
    Inventors: Stephen M. Cea, Roza Kotlyar, Jack T. Kavalieros, Martin D. Giles, Tahir Ghani, Kelin J. Kuhn, Markus Kuhn, Nancy M. Zelick
  • Patent number: 8551555
    Abstract: Biocompatible coatings for implantable medical devices are disclosed. Embodiments of the invention provide methods for coating an object with a biocompatible coating wherein the device is suspended using a flowing gas during the coating process. Embodiments of the invention provide tropoelastin coatings and methods of creating tropoelastin coatings for implantable medical devices. Optionally, the biocompatible coating can be a drug eluting coating.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: October 8, 2013
    Assignee: Intel Corporation
    Inventors: John Burghard, Carmen Campbell, Todd R. Younkin, Markus Kuhn, David Shykind, Jose Maiz
  • Patent number: 8487348
    Abstract: The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming isolation structures in strained semiconductor bodies of non-planar transistors while maintaining strain in the semiconductor bodies.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: July 16, 2013
    Assignee: Intel Corporation
    Inventors: Stephen M. Cea, Martin D. Giles, Kelin Kuhn, Jack T. Kavalieros, Markus Kuhn
  • Publication number: 20120305990
    Abstract: The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming isolation structures in strained semiconductor bodies of non-planar transistors while maintaining strain in the semiconductor bodies.
    Type: Application
    Filed: August 17, 2012
    Publication date: December 6, 2012
    Inventors: Stephen M Cea, Martin D. Giles, Kelin Kuhn, Jack T. Kavalieros, Markus Kuhn
  • Patent number: 8299617
    Abstract: Described is a method and apparatus for forming interconnects with a metal-metal oxide electromigration barrier and etch-stop. In one embodiment of the invention, the method includes depositing a metal layer on the top of a planarized interconnect layer, the interconnect layer having an interlayer dielectric (ILD) with a top that is planar with the top of an electrically conductive interconnect. In one embodiment of the invention, the method includes reacting the metal layer with the ILD to form a metal oxide layer on the top of the ILD. At the same time, the metal layer will not be significantly oxidized by the electrically conductive interconnect, thus forming a metal barrier on the electrically conductive interconnect to improve electromigration performance. The metal barrier and metal oxide layer together comprise a protective layer. A second ILD may be subsequently formed on the protective layer, and the protective layer may act an etch-stop during a subsequent etch of the second ILD.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: October 30, 2012
    Assignee: Intel Corporation
    Inventors: Xiaorong Morrow, Jihperng Leu, Markus Kuhn, Jose A. Maiz
  • Publication number: 20120241818
    Abstract: Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.
    Type: Application
    Filed: June 4, 2012
    Publication date: September 27, 2012
    Inventors: Jack T. Kavalieros, Nancy Zelick, Been-Yih Jin, Markus Kuhn, Stephen M. Cea
  • Patent number: 8269283
    Abstract: The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming isolation structures in strained semiconductor bodies of non-planar transistors while maintaining strain in the semiconductor bodies.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: September 18, 2012
    Assignee: Intel Corporation
    Inventors: Stephen M. Cea, Martin D. Giles, Kelin Kuhn, Jack T. Kavalieros, Markus Kuhn
  • Patent number: 8211772
    Abstract: Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: July 3, 2012
    Assignee: Intel Corporation
    Inventors: Jack T. Kavalieros, Nancy M. Zelick, Been-Yih Jin, Markus Kuhn, Stephen M. Cea
  • Publication number: 20120091542
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include introducing a first metal source, a second metal source and an oxygen source into a chamber and then forming a ternary oxide film comprising a first percentage of the first metal, a second percentage of the second metal, and a third percentage of oxygen.
    Type: Application
    Filed: December 19, 2011
    Publication date: April 19, 2012
    Inventors: Mark R. Brazier, Matthew V. Metz, Michael L. McSwiney, Markus Kuhn, Michael L. Hattendorf
  • Publication number: 20120074464
    Abstract: A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.
    Type: Application
    Filed: September 23, 2010
    Publication date: March 29, 2012
    Inventors: Stephen M. Cea, Roza Kotlyar, Jack T. Kavalieros, Martin D. Giles, Tahir Ghani, Kelin J. Kuhn, Markus Kuhn, Nancy M. Zelick
  • Publication number: 20110253344
    Abstract: A protective structure, comprising a first material region having a surface facing the exterior and an inner boundary surface, wherein channels for conducting fluid are disposed between the outer surface and the inner boundary surface, and a second material region, which is thermally connected at least in sub-regions to the inner boundary surface of the first material region and which is porous, wherein in pores a reaction medium and/or cooling medium is stored and channels for conducting fluid extend as far as the inner boundary surface of the first material region.
    Type: Application
    Filed: May 5, 2011
    Publication date: October 20, 2011
    Applicant: Deutsches Zentrum fuer Luft- und Raumfahrt e.V.
    Inventors: Markus Kuhn, Hermann Hald, Waldemar Rotaermel
  • Publication number: 20110147847
    Abstract: The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming isolation structures in strained semiconductor bodies of non-planar transistors while maintaining strain in the semiconductor bodies.
    Type: Application
    Filed: December 21, 2009
    Publication date: June 23, 2011
    Inventors: Stephen M. Cea, Martin D. Giles, Kelin Kuhn, Jack T. Kavalieros, Markus Kuhn
  • Publication number: 20110147811
    Abstract: Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Inventors: Jack T. Kavalieros, Nancy Zelick, Been-Yih Jin, Markus Kuhn, Stephen M. Cea
  • Publication number: 20100219529
    Abstract: Described is a method and apparatus for forming interconnects with a metal-metal oxide electromigration barrier and etch-stop. In one embodiment of the invention, the method includes depositing a metal layer on the top of a planarized interconnect layer, the interconnect layer having an interlayer dielectric (ILD) with a top that is planar with the top of an electrically conductive interconnect. In one embodiment of the invention, the method includes reacting the metal layer with the ILD to form a metal oxide layer on the top of the ILD. At the same time, the metal layer will not be significantly oxidized by the electrically conductive interconnect, thus forming a metal barrier on the electrically conductive interconnect to improve electromigration performance. The metal barrier and metal oxide layer together comprise a protective layer. A second ILD may be subsequently formed on the protective layer, and the protective layer may act an etch-stop during a subsequent etch of the second ILD.
    Type: Application
    Filed: April 19, 2010
    Publication date: September 2, 2010
    Inventors: Xiaorong Morrow, Jihperng Leu, Markus Kuhn, Jose A. Maiz
  • Patent number: 7727892
    Abstract: Described is a method and apparatus for forming interconnects with a metal-metal oxide electromigration barrier and etch-stop. In one embodiment of the invention, the method includes depositing a metal layer on the top of a planarized interconnect layer, the interconnect layer having an interlayer dielectric (ILD) with a top that is planar with the top of an electrically conductive interconnect. In one embodiment of the invention, the method includes reacting the metal layer with the ILD to form a metal oxide layer on the top of the ILD. At the same time, the metal layer will not be significantly oxidized by the electrically conductive interconnect, thus forming a metal barrier on the electrically conductive interconnect to improve electromigration performance. The metal barrier and metal oxide layer together comprise a protective layer. A second ILD may be subsequently formed on the protective layer, and the protective layer may act an etch-stop during a subsequent etch of the second ILD.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: June 1, 2010
    Assignee: Intel Corporation
    Inventors: Xiaorong Morrow, Jihperng Leu, Markus Kuhn, Jose A. Maiz