Patents by Inventor Markus Naujok
Markus Naujok has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9401322Abstract: A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.Type: GrantFiled: July 25, 2011Date of Patent: July 26, 2016Assignee: Infineon Technologies AGInventors: Markus Naujok, Hermann Wendt, Alois Gutmann, Muhammed Shafi Pallachalil
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Patent number: 9373596Abstract: A structure and method of forming passivated copper chip pads is described. In various embodiments, the invention describes a substrate that includes active circuitry and metal levels disposed above the substrate. A passivation layer is disposed above a last level of the metal levels. A conductive liner is disposed in the sidewalls of an opening disposed in the passivation layer, wherein the conductive liner is also disposed over an exposed surface of the last level of the metal levels.Type: GrantFiled: June 17, 2014Date of Patent: June 21, 2016Assignee: Infineon Technologies AGInventors: Thomas Goebel, Erdem Kaltalioglu, Markus Naujok
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Publication number: 20140295661Abstract: A structure and method of forming passivated copper chip pads is described. In various embodiments, the invention describes a substrate that includes active circuitry and metal levels disposed above the substrate. A passivation layer is disposed above a last level of the metal levels. A conductive liner is disposed in the sidewalls of an opening disposed in the passivation layer, wherein the conductive liner is also disposed over an exposed surface of the last level of the metal levels.Type: ApplicationFiled: June 17, 2014Publication date: October 2, 2014Inventors: Thomas Goebel, Erdem Kaltalioglu, Markus Naujok
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Patent number: 8822324Abstract: A structure and method of forming passivated copper chip pads is described. In various embodiments, the invention describes a substrate that includes active circuitry and metal levels disposed above the substrate. A passivation layer is disposed above a last level of the metal levels. A conductive liner is disposed in the sidewalls of an opening disposed in the passivation layer, wherein the conductive liner is also disposed over an exposed surface of the last level of the metal levels.Type: GrantFiled: April 1, 2013Date of Patent: September 2, 2014Assignee: Infineon Technologies AGInventors: Thomas Goebel, Erdem Kaltalioglu, Markus Naujok
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Patent number: 8148235Abstract: Methods of forming air gaps between interconnects of integrated circuits and structures thereof are disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.Type: GrantFiled: November 13, 2009Date of Patent: April 3, 2012Assignee: Infineon Technologies AGInventors: Markus Naujok, Hermann Wendt, Alois Gutmann, Muhammed Shafi Pallachalil
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Publication number: 20110278730Abstract: A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.Type: ApplicationFiled: July 25, 2011Publication date: November 17, 2011Applicant: Infineon Technologies AGInventors: Markus Naujok, Hermann Wendt, Alois Gutmann
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Patent number: 8013364Abstract: A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.Type: GrantFiled: October 15, 2009Date of Patent: September 6, 2011Assignee: Infineon Technologies AGInventors: Markus Naujok, Hermann Wendt, Alois Gutmann, Muhammed Shafi Pallachalil
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Publication number: 20100144112Abstract: Methods of forming air gaps between interconnects of integrated circuits and structures thereof are disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.Type: ApplicationFiled: November 13, 2009Publication date: June 10, 2010Inventors: Markus Naujok, Hermann Wendt, Alois Gutmann, Muhammed Shafi Pallachalil
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Publication number: 20100032841Abstract: A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.Type: ApplicationFiled: October 15, 2009Publication date: February 11, 2010Inventors: Markus Naujok, Hermann Wendt, Alois Gutmann, Muhammed Shafi Pallachalil
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Patent number: 7629225Abstract: Methods of forming air gaps between interconnects of integrated circuits and structures thereof are disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.Type: GrantFiled: June 13, 2005Date of Patent: December 8, 2009Assignee: Infineon Technologies AGInventors: Markus Naujok, Hermann Wendt, Alois Gutmann, Muhammed Shafi Pallachalil
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Publication number: 20090200675Abstract: A structure and method of forming passivated copper chip pads is described. In various embodiments, the invention describes a substrate that includes active circuitry and metal levels disposed above the substrate. A passivation layer is disposed above a last level of the metal levels. A conductive liner is disposed in the sidewalls of an opening disposed in the passivation layer, wherein the conductive liner is also disposed over an exposed surface of the last level of the metal levels.Type: ApplicationFiled: February 11, 2008Publication date: August 13, 2009Inventors: Thomas Goebel, Erdem Kaltalioglu, Markus Naujok
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Patent number: 7282451Abstract: Methods of forming metal interconnect layers include forming an electrically insulating layer having a contact hole therein, on a semiconductor substrate and then forming a recess in the electrically insulating layer, at a location adjacent the contact hole. The contact hole and the recess are then filled with a first electrically conductive material (e.g., tungsten (W)). At least a portion of the first electrically conductive material within the contact hole is then exposed. This exposure occurs by etching back a portion of the electrically insulating layer using the first electrically conductive material within the contact hole and within the recess as an etching mask. The first electrically conductive material within the recess is then removed to expose another portion of the electrically insulating layer. Following this, the exposed portion of the first electrically conductive material is covered with a second electrically conductive material (e.g.Type: GrantFiled: August 31, 2005Date of Patent: October 16, 2007Assignees: Samsung Electronics Co., Ltd., Infineon Technologies AGInventors: Duk Ho Hong, Kyoung Woo Lee, Markus Naujok, Roman Knoefler
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Patent number: 7201634Abstract: Apparatus for and methods of chemical mechanical polishing (CMP) of semiconductor wafers are disclosed. A preferred embodiment comprises an apparatus for polishing a semiconductor workpiece that includes a polishing pad, a fluid dispenser adapted to dispense a fluid to the polishing pad, and a temperature measurement device adapted to measure the temperature of the fluid. The apparatus includes a heat exchanger adapted to increase or decrease the temperature of the fluid.Type: GrantFiled: November 14, 2005Date of Patent: April 10, 2007Assignee: Infineon Technologies AGInventors: Markus Naujok, Erdem Kaltalioglu
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Publication number: 20070045123Abstract: Methods of forming metal interconnect layers include forming an electrically insulating layer having a contact hole therein, on a semiconductor substrate and then forming a recess in the electrically insulating layer, at a location adjacent the contact hole. The contact hole and the recess are then filled with a first electrically conductive material (e.g., tungsten (W)). At least a portion of the first electrically conductive material within the contact hole is then exposed. This exposure occurs by etching back a portion of the electrically insulating layer using the first electrically conductive material within the contact hole and within the recess as an etching mask. The first electrically conductive material within the recess is then removed to expose another portion of the electrically insulating layer. Following this, the exposed portion of the first electrically conductive material is covered with a second electrically conductive material (e.g.Type: ApplicationFiled: August 31, 2005Publication date: March 1, 2007Inventors: Duk Hong, Kyoung Lee, Markus Naujok, Roman Knoefler
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Publication number: 20060281295Abstract: Methods of forming air gaps between interconnects of integrated circuits and structures thereof are disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.Type: ApplicationFiled: June 13, 2005Publication date: December 14, 2006Inventors: Markus Naujok, Hermann Wendt, Alois Gutmann, Muhammed Shafi Pallachalil
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Patent number: 7091612Abstract: A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.Type: GrantFiled: October 14, 2003Date of Patent: August 15, 2006Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Kaushik Kumar, Timothy Dalton, Larry Clevenger, Andy Cowley, Douglas C. La Tulipe, Mark Hoinkis, Chih-Chao Yang, Yi-Hsiung Lin, Erdem Kaltalioglu, Markus Naujok, Jochen Schacht
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Patent number: 7041574Abstract: A method of forming a composite intermetal dielectric structure is provided. An initial intermetal dielectric structure is provided, which includes a first dielectric layer and two conducting lines. The two conducting lines are located in the first dielectric layer. A portion of the first dielectric layer is removed between the conducting lines to form a trench. The trench is filled with a second dielectric material. The second dielectric material is a low-k dielectric having a dielectric constant less than that of the first dielectric layer.Type: GrantFiled: July 19, 2004Date of Patent: May 9, 2006Assignee: Infineon Technologies AGInventors: Sun-Oo Kim, Markus Naujok, Andy Cowley
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Publication number: 20060079159Abstract: Chemical mechanical polish (CMP) devices, CMP systems, methods of CMP, and methods of manufacturing CMP devices. A CMP device comprises a plurality of zones, with each zone having a matrix of fixed abrasive features disposed therein. The abrasive-containing matrix within each zone has material removal properties that differ from the material removal properties of the abrasive-containing matrixes of the other zones. The material removal property differences of the abrasive-containing matrixes of the zones may achieved by using different abrasive materials, densities, heights, or shapes, or combinations thereof, of the fixed abrasive features within the zones, or by using physical or chemical conditioning. When the novel CMP device is used to planarize a semiconductor wafer, a substantially planar surface with an improved CMP profile results.Type: ApplicationFiled: October 8, 2004Publication date: April 13, 2006Inventors: Markus Naujok, Laertis Economikos
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Publication number: 20050077628Abstract: A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.Type: ApplicationFiled: October 14, 2003Publication date: April 14, 2005Inventors: Kaushik Kumar, Timothy Dalton, Larry Clevenger, Andy Cowley, Douglas La Tulipe, Mark Hoinkis, Chih-Chao Yang, Yi-Hsiung Lin, Erdem Kaltalioglu, Markus Naujok, Jochen Schacht
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Publication number: 20040259273Abstract: A method of forming a composite intermetal dielectric structure is provided. An initial intermetal dielectric structure is provided, which includes a first dielectric layer and two conducting lines. The two conducting lines are located in the first dielectric layer. A portion of the first dielectric layer is removed between the conducting lines to form a trench. The trench is filled with a second dielectric material. The second dielectric material is a low-k dielectric having a dielectric constant less than that of the first dielectric layer.Type: ApplicationFiled: July 19, 2004Publication date: December 23, 2004Inventors: Sun-Oo Kim, Markus Naujok, Andy Cowley