Passivated Copper Chip Pads
A structure and method of forming passivated copper chip pads is described. In various embodiments, the invention describes a substrate that includes active circuitry and metal levels disposed above the substrate. A passivation layer is disposed above a last level of the metal levels. A conductive liner is disposed in the sidewalls of an opening disposed in the passivation layer, wherein the conductive liner is also disposed over an exposed surface of the last level of the metal levels.
This invention relates generally to electronic devices, and more particularly to passivated copper chip pads.
BACKGROUNDA flip chip package includes a direct electrical connection of face down (“flipped”) semiconductor components onto substrates or carriers, such as ceramic substrates, or circuit boards. The flip chip semiconductor components are predominantly semiconductor devices, however, components such as passive filters, detector arrays, and MEM devices are also being used in flip chip form. The use of flip chip packaging has dramatically grown as a result of the flip chips advantages in size, performance, flexibility, reliability, and cost over other packaging methods and from the widening availability of flip chip materials, equipment and services.
Flip chips are advantageous because of their high-speed electrical performance, when compared to other assembly methods. For example, eliminating bond wires reduces the delay in inductance and capacitance of the connection, and substantially shortens the current path resulting in a high speed off-chip interconnection. Flip chips also provide the greatest input/output connection flexibility. Wire bond connections are generally limited to the perimeter of the chip or die, driving the die sizes up as a number of connections have increased over the years. Flip chip connections can use the whole area of the die, accommodating many more connections on a smaller die. Further, flip chips are amenable to 3-D integration by stacking over other flip chips or other components.
For almost 25 years, the semiconductor industry has rolled out a new generation of technology that has delivered improved performance at lower costs. One of the challenges faced in semiconductor manufacturing relates to reduction in process costs with each subsequent technology generation. Consequently, packaging processes also need to reduce fabrication costs with each technology generation. Hence, what are needed in the art are improved structures and methods for producing flip chip packages at lower costs.
SUMMARY OF THE INVENTIONThese and other problems are generally solved or circumvented, and technical advantages are generally achieved, by embodiments of the present invention which provide flip chip and methods of manufacture thereof.
Embodiments of the invention include methods and structures of passivated copper chip pads. In accordance with an embodiment of the present invention, the structure includes a substrate comprising active circuitry, and metal levels disposed above the substrate. A passivation layer is disposed above a last level of the metal levels. A conductive liner is disposed in the sidewalls of a trench disposed in the passivation layer, wherein the conductive liner is also disposed over an exposed surface of the last level of the metal levels.
The foregoing has outlined rather broadly the features of an embodiment of the present invention in order that the detailed description of embodiments of the invention that follows may be better understood. Additional features and advantages of embodiments of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTSThe making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
The present invention will be described with respect to preferred embodiments in a specific context, namely formation and design of flip chip packaging. The invention may also be applied, however, to other semiconductor components comprising, for example, other packaging such as wirebond packaging, embedded wafer level packaging, and ball grid array packaging. One of ordinary skill in the art will be able to recognize further examples as well.
Formation of flip chip packaging requires use of many lithographic steps for formation of the different levels of the package. This requires the use of expensive masks and lithography tools that increase the cost of the process. In various embodiments, the present invention overcomes these limitations by reducing the number of mask steps or number of masks needed in the fabrication of flip chips packages. Various embodiments of the invention achieve this by avoiding pad metallization or formation of chip bonding pads over the last metal level. Avoiding this process eliminates mask steps not only in their formation, but also mask steps in forming passivation layers above these chip bonding pads.
A structural embodiment of the invention will be first described using
An embodiment of the invention is illustrated in
A method of fabricating the flip chip package is now described in
A layer of photoresist is deposited over the optional insulating liner 140 (not shown). The photoresist is exposed and etched to form a mask layer. Using the photoresist mask layer, the optional insulating liner 140, passivation layer 130, and the cap layer 120 are etched to open a trench 150 (or a via) (
Referring to
As illustrated in
A photo resist layer 180 is deposited over the UBM layer 170, as illustrated in
Referring to
In a different embodiment, a flip chip package is formed after the removal of the exposed UBM layer 170, as described in
An embodiment of the invention for manufacturing the package is next described using
As illustrated in
Although embodiments of the present invention are explained for flip chip packages, the embodiments of the invention apply to other packages, in particular to wire bonding, wafer level, and embedded wafer level packages.
Although embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present invention.
1 Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims
1-16. (canceled)
17. A flip chip package comprising:
- metallization comprising metal levels disposed above a substrate, the substrate comprising active circuitry;
- a cap layer disposed above a last level of the metal levels;
- a passivation layer disposed above the cap layer;
- a nitride layer disposed above the passivation layer, wherein an opening is disposed in the nitride layer, the passivation layer and the cap layer; and
- a conductive liner disposed in sidewalls of the opening and over an exposed surface of the last level of the metal levels.
18. The flip chip package of claim 17, wherein the conductive liner comprises a material selected from the group consisting of TiN, TaN, Ti/TiN, Ta, Ta/TaN, and Al/Cu.
19. The flip chip package of claim 17, wherein the passivation layer comprises an oxide layer.
20. The flip chip package of claim 17, wherein the last level of the metal levels comprises copper, wherein the last level of the metal levels is embedded in an inter level dielectric layer.
21. The flip chip package of claim 17, further comprising:
- an under bump metallization layer disposed over the conductive liner; and
- a solder bump disposed above the under bump metallization layer.
22. The flip chip package of claim 21, wherein the solder bump comprises an eutectic 63Sn:37Pb, 5Sn:95Pb, or an Sn:Ag alloy, and wherein the under bump metallization layer comprises layers comprising Ti/Cu/Ni.
23. (canceled)
24. A passivated copper chip pad comprising:
- metallization comprising metal levels disposed above a substrate, the substrate comprising active circuitry;
- a cap layer disposed above a last level of the metal levels;
- a passivation layer disposed above the cap layer;
- a nitride layer disposed above the passivation layer;
- an opening disposed in the nitride layer, the passivation layer, and the cap layer; and
- a conductive liner disposed in sidewalls of the opening and over an exposed surface of the last level of the metal levels.
25. The passivated copper chip pad of claim 24, further comprising:
- an under bump metallization layer disposed over the conductive liner; and
- a solder bump disposed above the under bump metallization layer.
26. The passivated copper chip pad of claim 24, wherein the last level of the metal levels comprises copper, wherein the last level of the metal levels is embedded in an inter level dielectric layer.
27. The passivated copper chip pad of claim 24, wherein the solder bump comprises an eutectic 63Sn:37Pb, 5Sn:95Pb, or an Sn:Ag alloy, and wherein the under bump metallization layer comprises layers comprising Ti/Cu/Ni.
28. The flip chip package of claim 17, wherein the cap layer comprises a nitride material.
29. A flip chip package comprising:
- metallization comprising metal levels disposed above a substrate, the substrate comprising active circuitry;
- a cap layer disposed above a last level of the metal levels;
- a passivation layer disposed above the cap layer;
- an opening disposed in the passivation layer and the cap layer; and
- a conductive liner disposed over the last level of the metal levels and along the sidewalls of the opening wherein the conductive liner extends above a top surface of the passivation layer and does not overlie a horizontal surface of the passivation layer.
30. The flip chip package of claim 29, wherein the conductive liner comprises a material selected from the group consisting of TiN, TaN, Ti/TiN, Ta, Ta/TaN, and Al/Cu.
31. The flip chip package of claim 29, wherein the passivation layer is selected from the group consisting of an oxide, FTEOS, SiN and SiCOH.
32. The flip chip package of claim 29, wherein the last level of the metal levels comprises copper, wherein the last level of the metal levels is embedded in an inter level dielectric layer.
33. The flip chip package of claim 29, further comprising:
- an under bump metallization layer disposed over the conductive liner; and
- a solder bump disposed above the under bump metallization layer.
34. The flip chip package of claim 21, wherein the solder bump is bonded to a PC board.
Type: Application
Filed: Feb 11, 2008
Publication Date: Aug 13, 2009
Inventors: Thomas Goebel (Munich), Erdem Kaltalioglu (Newburgh, NY), Markus Naujok (Dresden)
Application Number: 12/029,127
International Classification: H01L 23/48 (20060101); H01L 21/00 (20060101); H01L 21/44 (20060101);