Abstract: Various implementations described herein are directed to a method for manufacturing an integrated circuit. The method may include defining multiple lithographic regions for the integrated circuit, and the multiple lithographic regions may include a first lithographic region and a second lithographic region. The method may include defining an anchor in the first lithographic region and defining a target in the second lithographic region. The method may include defining a spacing interval between the anchor and the target. The method may include inserting an integration fill in the spacing interval.

Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell.

Abstract: Various implementations described herein are directed to an apparatus having a receiver module that receives a floorplan of an integrated circuit having power gates, an obstruction, and a control pin for providing a sleep signal. The apparatus may include an identifier module that identifies where the obstruction interrupts a sequence of the power gates, organizes the sequence of the power gates into a column, and divides the column into segments in which a first segment lies below the obstruction, a second segment lies above the obstruction, and a third segment is offset from the first and second segments. The apparatus may include a stitcher module that performs sleep signal stitching for the integrated circuit by distributing a sleep signal from the control pin to the power gates that includes each power gate in each of the first, second, and third segments.

Abstract: Various implementations described herein are directed to an apparatus. The apparatus may include a region identifier module that receives a floorplan of an integrated circuit, identifies a standard cell region between already placed functional blocks of the floorplan, and sub-divides the standard cell region into multiple sub-regions. The apparatus may include a region analyzer module that analyzes each sub-region of the multiple sub-regions to determine a number of already placed power straps that exist within a boundary of each sub-region. The apparatus may include a strap placement module that inserts one or more additional power straps in each sub-region based on user defined parameters for each sub-region, if it is determined that the number of already placed power straps is inconsistent with the user defined parameters for each sub-region.

Abstract: An apparatus, a method, and a method of manufacturing an integrated circuit having a metal layer, metal wires within the metal layer being configured such that they have a regular pattern.

Abstract: A static timing analysis method and apparatus that determine an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.

Abstract: Various implementations described herein are directed to an integrated circuit with mitigated resistance. The integrated circuit may include a cell having a plurality of transistors including a first transistor of a first type and a second transistor of a second type that is different from the first type. The integrated circuit may include a first wire coupling the first transistor to the second transistor. The integrated circuit may include a second wire coupling the first wire to an output routing wire. The integrated circuit may include a redundant wire further coupling the first wire to the output routing wire.

Abstract: A static timing analysis method and apparatus that determine an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.

Abstract: Various implementations described herein are directed to an integrated circuit with mitigated resistance. The integrated circuit may include a cell having a plurality of transistors including a first transistor of a first type and a second transistor of a second type that is different from the first type. The integrated circuit may include a first wire coupling the first transistor to the second transistor. The integrated circuit may include a second wire coupling the first wire to an output routing wire. The integrated circuit may include a redundant wire further coupling the first wire to the output routing wire.

Abstract: A static timing analysis method that determines an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.

Abstract: An integrated circuit 2 is formed with standard-cell power conductors 14 which are overlaid by power grid conductors 20. The power grid conductors are offset in a direction transverse to the longitudinal axis of the power grid conductors relative to their underlying standard-cell power conductor. This has the effect of increasing the conductor spacing possible to one side of the power grid conductor. Accordingly, a wider than minimum width power grid conductor may be provided which blocks only one of its adjacent track positions from being used by a routing conductor 22.

Abstract: An integrated circuit layout includes a routing layout of routing conductors and routing connection vias formed prior to a power grid connection which forms power connection vias between power grid conductors and standard-power cell conductors within the standard cells. This enables a minimum via spacing requirement to be met while permitting an increased flexibility in the positioning of the routing connection vias.

Abstract: A static timing analysis method that determines an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.

Abstract: An integrated circuit layout is formed by performing a routing step forming a routing layout of routing conductors and routing connection vias prior to performing a power grid connection step which forms power connection vias between power grid conductors and standard-power cell conductors within the standard cells. This enables a minimum via spacing requirement to be met while permitting an increased flexibility in the positioning of the routing connection vias.

Abstract: An integrated circuit 2 has data processing circuitry processing a data signal passing along a data path 14. Clocked circuitry coupled to the data processing circuitry serves to regulate passage of the data signal along the data path. The data signal is supplied at a data signal voltage amplitude and the clock signal is supplied at a different clock signal voltage amplitude. The clock signal voltage amplitude is higher than the data signal voltage amplitude. A separate clock signal power supply grid 12 is provided in addition to the data power supply grid 10.

Abstract: An integrated circuit 2 is formed with standard-cell power conductors 14 which are overlaid by power grid conductors 20. The power grid conductors are offset in a direction transverse to the longitudinal axis of the power grid conductors relative to their underlying standard-cell power conductor. This has the effect of increasing the conductor spacing possible to one side of the power grid conductor. Accordingly, a wider than minimum width power grid conductor may be provided which blocks only one of its adjacent track positions from being used by a routing conductor 22.

Abstract: An integrated circuit layout 2 is formed by performing a routing step forming a routing layout of routing conductors 26 and routing connection vias 28 prior to performing a power grid connection step which forms power connection vias 24 between power grid conductors 22 and standard-power cell conductors 20 within the standard cells 6. This enables a minimum via spacing requirement to be met whilst permitting an increased flexibility in the positioning of the routing connection vias.

Abstract: An integrated circuit 2 has data processing circuitry processing a data signal passing along a data path 14. Clocked circuitry coupled to the data processing circuitry serves to regulate passage of the data signal along the data path. The data signal is supplied at a data signal voltage amplitude and the clock signal is supplied at a different clock signal voltage amplitude. The clock signal voltage amplitude is higher than the data signal voltage amplitude. A separate clock signal power supply grid 12 is provided in addition to the data power supply grid 10.

Abstract: A method of generating an integrated circuit layout comprises a step of determining a placement of standard cells selected from a standard cell library while permitting boundary conflicts in which incompatible boundary regions of standard cells are placed next to each other. After determining routing connections between the standard cells, the integrated circuit layout is generated. The generation of the integrated circuit layout includes a mapping step of mapping at least one incompatible boundary region to an alternative boundary region to resolve at least one boundary conflict.

Abstract: A data storage circuit for receiving and holding a data value includes an input stage configured to receive a data value in response to the precharge phase changing to an evaluation phase and to hold the data value during the evaluation phase. An output stage has an output latching element for holding the value, two switching devices for updating the output latching element and an output. The switching devices each being controlled by respective signals from dual data lines, wherein, in response to the data value held in the input stage being a logical one, the first switching device updates the output latching element with a value indicative of the logical one and in response to the data value held in the input stage being a logical zero, the second switching device updates the output latching element with a value indicative of the logical zero.