Abstract: A method of generating a layout of an integrated circuit is disclosed, the layout incorporating both standard cells and at least one memory instance generated by a memory compiler to define a memory device of the integrated circuit. Input data is received specifying one or more properties of a desired memory instance. The memory compiler generates the desired memory instance based on the input data and using the specified memory architecture. A standard cell library is provided. The memory compiler references at least one property of the standard cell library in order to generate the desired memory instance. The layout is then generated by populating standard cell rows with standard cells selected from the standard cell library in order to provide the functional components required by the integrated circuit, and integrating into the layout the desired memory instance provided by the memory compiler.

Abstract: A method of generating a layout of an integrated circuit is disclosed, the layout incorporating both standard cells and at least one memory instance generated by a memory compiler to define a memory device of the integrated circuit. Input data is received specifying one or more properties of a desired memory instance. The memory compiler generates the desired memory instance based on the input data and using the specified memory architecture. A standard cell library is provided. The memory compiler references at least one property of the standard cell library in order to generate the desired memory instance. The layout is then generated by populating standard cell rows with standard cells selected from the standard cell library in order to provide the functional components required by the integrated circuit, and integrating into the layout the desired memory instance provided by the memory compiler.

Abstract: A state retention circuit is provided comprising a pulse generator which is configured in a non-retention mode of operation to be responsive to a clock signal to periodically assert a pulse, and a storage structure that comprises a storage element for storing state and an isolation structure for responding to the asserted pulse. In particular, the isolation structure is responsive to the asserted pulse to cause the storage element to update its stored state dependent on an input to the storage structure. Conversely, in the absence of the asserted pulse, the isolation structure isolates the storage element from the input. The pulse generator can be driven by a retention control signal to enter a retention mode of operation, during which it does not assert the pulse irrespective of changes in the clock signal.

Abstract: A power control apparatus for controlling a supply voltage for an associated circuit comprises a power input for receiving an input voltage and a power output for supplying the supply voltage to the circuit. A switch device is provided with a first terminal coupled to the power input, a second terminal coupled to the power output and a control terminal for receiving a sleep select signal. A control device selectively configures the switch device to act as either a power gating switch, in which the switch device is responsive to the sleep select signal to select whether or not to supply the input voltage to the power output; or a retention switch in which a voltage difference is formed between the power input and the power input and the switch device supplies a retention voltage to the power output, the retention voltage being different to the input voltage.

Abstract: A data storage circuit for receiving and holding a data value includes an input stage configured to receive a data value in response to the precharge phase changing to an evaluation phase and to hold the data value during the evaluation phase. An output stage has an output latching element for holding the value, two switching devices for updating the output latching element and an output. The switching devices each being controlled by respective signals from dual data lines, wherein, in response to the data value held in the input stage being a logical one, the first switching device updates the output latching element with a value indicative of the logical one and in response to the data value held in the input stage being a logical zero, the second switching device updates the output latching element with a value indicative of the logical zero.

Abstract: A clock gating circuitry is configured to receive a clock signal and to output an output signal comprising either the clock signal or the predetermined gated value. The circuitry receives a clock signal, a clock enable signal having either an enable value or a disable value, and a power mode signal having either a low power value (indicating entry to a low power mode in which at least a portion of the plurality of synchronous elements are powered to retain data and are not clocked and at least a further portion of the plurality of synchronous elements are powered down), or a functional mode value (indicating the plurality of synchronous elements are to be powered). A clock gating unit has logic circuitry that is configured to output the clock signal or the predetermined gated value depending upon the low power value and the functional mode value.

Abstract: A clock gating circuitry unit for supplying either a clock signal or a predetermined gated value to a plurality of synchronous elements within an integrated circuit is disclosed. The clock gating circuitry is configured to receive a clock signal and to output an output signal comprising either the clock signal or the predetermined gated value.

Abstract: A power control apparatus for controlling a supply voltage for an associated circuit comprises a power input for receiving an input voltage and a power output for supplying the supply voltage to the circuit. A switch device is provided with a first terminal coupled to the power input, a second terminal coupled to the power output and a control terminal for receiving a sleep select signal. A control device selectively configures the switch device to act as either a power gating switch, in which the switch device is responsive to the sleep select signal to select whether or not to supply the input voltage to the power output; or a retention switch in which a voltage difference is formed between the power input and the power input and the switch device supplies a retention voltage to the power output, the retention voltage being different to the input voltage.

Abstract: A state retention circuit is provided comprising a pulse generator which is configured in a non-retention mode of operation to be responsive to a clock signal to periodically assert a pulse, and a storage structure that comprises a storage element for storing state and an isolation structure for responding to the asserted pulse. In particular, the isolation structure is responsive to the asserted pulse to cause the storage element to update its stored state dependent on an input to the storage structure. Conversely, in the absence of the asserted pulse, the isolation structure isolates the storage element from the input. The pulse generator can be driven by a retention control signal to enter a retention mode of operation, during which it does not assert the pulse irrespective of changes in the clock signal.

Abstract: The application discloses storage circuitry with a pulse generator used to control switches on two inputs to the storage circuitry thereby connecting either operational data or diagnostic data to the storage circuitry. Thus, the pulse generator selects the data paths by outputting pulses to a diagnostic output or to a functional output, and these pulses controlling the switches on the two inputs to the storage circuitry.

Abstract: Pipelining and parallel execution of multiple load instructions is performed within a load store unit. When a first load instruction incurs a cache miss and proceeds to retrieve the load data from the system memory hierarchy, a second load instruction addressing the same load data will be merged into the first load instruction so that the data returned from the system memory hierarchy is sent to register files associated with both the first and second load instructions. As a result, the second load instruction does not have to wait until the load data has been written and validated in the data cache.

Abstract: In a load/store unit within a microprocessor, load instructions are executed out of order. The load instructions are assigned tags in a predetermined manner, and then assigned to a load reorder queue for keeping track of the program order of the load instructions. Then when new load instructions are issued, the new load instructions are compared to entries within the load reorder queues to detect out of order problems.

Abstract: False transitions resulting from capacitive coupling between parallel interconnects driven by dynamic circuits are reduced by classifying interconnects based on the timing of expected data transitions in the signals they carry. Interconnects carrying signals expected to transition during a first portion of a processor cycle are treated as one category, while interconnects carrying signals expected to transition during a second, different portion of the processors cycle are treated as a second category. Interconnects of different categories are interdigitated, a resets of dynamic driving circuits are tuned so that, at any given time, alternate interconnects are “quiet” or stable. Therefore interconnects being driven with data transitions are directly adjacent to quiet lines, and foot devices are implemented as necessary to prevent coupling expected during the reset phase.

Abstract: A system and method for determining an age function by performing a logical function on each entry residing within a queue, determining when a particular one of the entries residing in the queue was stored in the queue relative to the other entries, and determining an oldest or youngest entry residing in the queue relative to the logical functions performed on each of the instructions. In one embodiment of the present invention, the entries are instructions temporarily stored within a queue in the processor. The logical function performed may determine which of the instructions is valid. The queue may be cyclical.

Abstract: Performance is increased within a dynamic multiplexer by removing the foot device and replacing it with a logic gate (such as an OR, NOR, or NAND gate) receiving the select signals and activating the precharge device within the dynamic multiplexer circuit. With such a configuration, crowbar current is still inhibited.

Abstract: A multiplier in a data processing system has a modified compressor structure which is configured to alleviate both a tendency of the multiplier to be wire bound and to optimize a circuit area required to implement the multiplier. In the modified compressor structure, all inputs to the compressor are not of the same weight, all outputs of the compressor are not of the same weight, and carry values generated during the compression process are no longer all shifted in a same direction. Instead, in the compressor, a mixture of sum values and carry values generated during a compression process are reduced within the compressor. By modifying the compressor so that it is no longer limited to receiving only inputs having a same weight, there is a reduced input/output signal requirement and, therefore, the compressor has less global interconnect requirements.