Abstract: A method for fabricating enhanced-mobility pFET devices having channel lengths below 50 nm. Gates for pFETs may be patterned in dense arrays on a semiconductor substrate that includes shallow trench isolation (STI) structures. Partially-enclosed voids in the semiconductor substrate may be formed at source and drain regions for the gates, and subsequently filled with epitaxially-grown semiconductor that compressively stresses channel regions below the gates. Some of the gates (dummy gates) may extend over edges of the STI structures to prevent undesirable faceting of the epitaxial material in the source and drain regions.

Abstract: A method for fabricating enhanced-mobility pFET devices having channel lengths below 50 nm. Gates for pFETs may be patterned in dense arrays on a semiconductor substrate that includes shallow trench isolation (STI) structures. Partially-enclosed voids in the semiconductor substrate may be formed at source and drain regions for the gates, and subsequently filled with epitaxially-grown semiconductor that compressively stresses channel regions below the gates. Some of the gates (dummy gates) may extend over edges of the STI structures to prevent undesirable faceting of the epitaxial material in the source and drain regions.

Abstract: The described process allows trenches to be etched in a structure comprising a support substrate and a multilayer, formed on the substrate, for the definition of wave guides of an integrated optical device and comprises a selective plasma attack in the multilayer through a masking structure that leaves uncovered areas of the multilayer corresponding to the trenches to be etched. Such a masking structure is obtained by forming a mask of metallic material on the multilayer that leaves uncovered the areas corresponding to the trenches to be etched and forming a mask of non-metallic material, for example photoresist, on it that leaves uncovered regions comprising at least part of the areas and an edge portion of the mask of metallic material.

Abstract: An embodiment of an integrated circuit includes first and second semiconductor layers and a contact region disposed in the second layer. The first semiconductor layer is of a first conductivity, and the second semiconductor layer is disposed over the first layer and has a surface. The contact region is contiguous with the surface, contacts the first layer, includes a first inner conductive portion, and includes an outer conductive portion of the first conductivity. The contact region may extend deeper than conventional contact regions, because where the inner conductive portion is formed from a trench, doping the outer conductive portion via the trench may allow one to implant the dopants more deeply than conventional techniques allow.

Abstract: An embodiment of an integrated circuit includes first and second semiconductor layers and a contact region disposed in the second layer. The first semiconductor layer is of a first conductivity, and the second semiconductor layer is disposed over the first layer and has a surface. The contact region is contiguous with the surface, contacts the first layer, includes a first inner conductive portion, and includes an outer conductive portion of the first conductivity. The contact region may extend deeper than conventional contact regions, because where the inner conductive portion is formed from a trench, doping the outer conductive portion via the trench may allow one to implant the dopants more deeply than conventional techniques allow.

Abstract: The described process allows trenches to be etched in a structure comprising a support substrate and a multilayer, formed on the substrate, for the definition of wave guides of an integrated optical device and comprises a selective plasma attack in the multilayer through a masking structure that leaves uncovered areas of the multilayer corresponding to the trenches to be etched. Such a masking structure is obtained by forming a mask of metallic material on the multilayer that leaves uncovered the areas corresponding to the trenches to be etched and forming a mask of non-metallic material, for example photoresist, on it that leaves uncovered regions comprising at least part of the areas and an edge portion of the mask of metallic material.

Abstract: A method for manufacturing an integrated electronic device. The method includes providing an SOI substrate having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor starting layer on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer on the insulating layer for integrating components of the device, and forming at least one contact trench extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.

Abstract: A method of fabricating a wafer-size photovoltaic cell module includes defining an integrated cellular structure of a light converting monolateral or bilateral junction diode in an epitaxially grown detachable layer including a first deposited metal current collecting terminal of the diode. The method also includes laminating onto the surface of the processed epitaxially grown detachable layer a film of an optical grade plastic material resistant to hydrofluoric acid solutions. The method further includes immersing the wafer in a hydrofluoric acid solution causing detachment of the epitaxially grown silicon layer laminated with the film, and polishing the surface of separation of the detached epitaxially grown layer and forming a second metal current collecting terminal of the diode by masked deposition of a metal at a temperature tolerable by the film.

Abstract: An embodiment of an integrated circuit includes first and second semiconductor layers and a contact region disposed in the second layer. The first semiconductor layer is of a first conductivity, and the second semiconductor layer is disposed over the first layer and has a surface. The contact region is contiguous with the surface, contacts the first layer, includes a first inner conductive portion, and includes an outer conductive portion of the first conductivity. The contact region may extend deeper than conventional contact regions, because where the inner conductive portion is formed from a trench, doping the outer conductive portion via the trench may allow one to implant the dopants more deeply than conventional techniques allow.

Abstract: An electronic device is proposed. The device is integrated in a chip including at least one stacked layer having a front surface and a rear surface opposite the front surface, the device including: an insulating trench insulating an active region of the chip, the insulating trench having a section across each plane parallel to the front surface extending along a longitudinal line, and a front-rear contact electrically contacting the front surface to the rear surface in the active region, wherein the section of the insulating trench has a non-uniform width along the longitudinal line, and/or the device further includes at least one further insulating trench within the active region.

Abstract: A method for manufacturing an integrated electronic device. The method includes providing an SOI substrate having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor starting layer on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer on the insulating layer for integrating components of the device, and forming at least one contact trench extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.

Abstract: A process for bonding two distinct substrates that integrate microsystems, including the steps of forming micro-integrated devices in at least one of two substrates using micro-electronic processing techniques and bonding the substrates. Bonding is performed by forming on a first substrate bonding regions of deformable material and pressing the substrates one against another so as to deform the bonding regions and to cause them to react chemically with the second substrate. The bonding regions are preferably formed by a thick layer of a material chosen from among aluminum, copper and nickel, covered by a thin layer of a material chosen from between palladium and platinum. Spacing regions ensure exact spacing between the two wafers.

Abstract: An embodiment of an integrated circuit includes first and second semiconductor layers and a contact region disposed in the second layer. The first semiconductor layer is of a first conductivity, and the second semiconductor layer is disposed over the first layer and has a surface. The contact region is contiguous with the surface, contacts the first layer, includes a first inner conductive portion, and includes an outer conductive portion of the first conductivity. The contact region may extend deeper than conventional contact regions, because where the inner conductive portion is formed from a trench, doping the outer conductive portion via the trench may allow one to implant the dopants more deeply than conventional techniques allow.

Abstract: An electronic device is proposed. The device is integrated in a chip including at least one stacked layer having a front surface and a rear surface opposite the front surface, the device including: an insulating trench insulating an active region of the chip, the insulating trench having a section across each plane parallel to the front surface extending along a longitudinal line, and a front-rear contact electrically contacting the front surface to the rear surface in the active region, wherein the section of the insulating trench has a non-uniform width along the longitudinal line, and/or the device further includes at least one further insulating trench within the active region.

Abstract: A method for manufacturing an integrated electronic device. The method includes providing an SOI substrate having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor starting layer on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer on the insulating layer for integrating components of the device, and forming at least one contact trench extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.

Abstract: A process for bonding two distinct substrates that integrate microsystems, including the steps of forming micro-integrated devices in at least one of two substrates using micro-electronic processing techniques and bonding the substrates. Bonding is performed by forming on a first substrate bonding regions of deformable material and pressing the substrates one against another so as to deform the bonding regions and to cause them to react chemically with the second substrate. The bonding regions are preferably formed by a thick layer of a material chosen from among aluminum, copper and nickel, covered by a thin layer of a material chosen from between palladium and platinum. Spacing regions ensure exact spacing between the two wafers.

Abstract: A method of fabricating a wafer-size photovoltaic cell module includes defining an integrated cellular structure of a light converting monolateral or bilateral junction diode in an epitaxially grown detachable layer including a first deposited metal current collecting terminal of the diode. The method also includes laminating onto the surface of the processed epitaxially grown detachable layer a film of an optical grade plastic material resistant to hydrofluoric acid solutions. The method further includes immersing the wafer in a hydrofluoric acid solution causing detachment of the epitaxially grown silicon layer laminated with the film, and polishing the surface of separation of the detached epitaxially grown layer and forming a second metal current collecting terminal of the diode by masked deposition of a metal at a temperature tolerable by the film.

Abstract: A waveguide includes a substrate, lower cladding having a decreasing cross-section, and a core having an increasing cross-section. The lower cladding is formed on a substrate, and the waveguide core is formed on the lower cladding. The waveguide core includes a first tract of constant thickness and a second tract of varying thickness, and finally side and upper cladding of the waveguide is formed. In order to obtain a waveguide having a segment of varying thickness in an easy, controlled and adiabatic manner, two series of operations are carried out to form the lower cladding and the core.

Abstract: The described process allows trenches to be etched in a structure comprising a support substrate and a multilayer, formed on the substrate, for the definition of wave guides of an integrated optical device and comprises a selective plasma attack in the multilayer through a masking structure that leaves uncovered areas of the multilayer corresponding to the trenches to be etched. Such a masking structure is obtained by forming a mask of metallic material on the multilayer that leaves uncovered the areas corresponding to the trenches to be etched and forming a mask of non-metallic material, for example photoresist, on it that leaves uncovered regions comprising at least part of the areas and an edge portion of the mask of metallic material.

Abstract: A process for manufacturing a semiconductor wafer integrating electronic devices and a structure for electromagnetic decoupling are disclosed. The method includes providing a wafer of semiconductor material having a substrate; forming a plurality of first mutually adjacent trenches, open on a first face of the wafer, which have a depth and a width and define walls); by thermal oxidation, completely oxidizing the walls and filling at least partially the first trenches, so as to form an insulating structure of dielectric material; and removing one portion of the substrate comprised between the insulating structure and a second face of the wafer, opposite to the first face of the wafer.