Patents by Inventor Marta Mottura

Marta Mottura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040152020
    Abstract: A method of producing a wave guide integrated in a substrate, includes the phases of forming a lower cladding of the guide supported by the substrate and forming a core of the guide by means of a doped material, the core extending along an axis of propagation and having a rounded cross section. The method is characterized in that said phase of forming the core includes the phases of attacking said lower cladding to define a concave region delimited by a curved surface and extending along the axis of propagation, and providing on a free surface of said lower cladding a layer of doped material filling the concave region to form a first portion of the core in contact with the curved surface.
    Type: Application
    Filed: December 22, 2003
    Publication date: August 5, 2004
    Inventors: Pietro Montanini, Luigi Di Turi, Ivana Favretto, Marta Mottura
  • Patent number: 6689627
    Abstract: A process for manufacturing components in a multi-layer wafer, including the steps of: providing a multi-layer wafer comprising a first semiconductor material layer, a second semiconductor material layer (, and a dielectric material layer arranged between the first and the second semiconductor material layer; and removing the first semiconductor material layer initially by mechanically thinning the first semiconductor material layer, so as to form a residual conductive layer, and subsequently by chemically removing the residual conductive layer. In one application, the multi-layer wafer is bonded to a first wafer of semiconductor material, with the second semiconductor material layer facing the first wafer, after micro-electromechanical structures have been formed in the second semiconductor material layer of the multi-layer wafer.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: February 10, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marta Mottura, Alessandra Fischetti, Marco Ferrera, Bernardino Zerbini, Mauro Bombonati
  • Publication number: 20030113981
    Abstract: A process for manufacturing a semiconductor wafer integrating electronic devices and a structure for electromagnetic decoupling are disclosed. The method includes providing a wafer of semiconductor material having a substrate; forming a plurality of first mutually adjacent trenches, open on a first face of the wafer, which have a depth and a width and define walls); by thermal oxidation, completely oxidizing the walls and filling at least partially the first trenches, so as to form an insulating structure of dielectric material; and removing one portion of the substrate comprised between the insulating structure and a second face of the wafer, opposite to the first face of the wafer.
    Type: Application
    Filed: October 29, 2002
    Publication date: June 19, 2003
    Applicant: STMicroelectronics S.r.I.
    Inventors: Chantal Combi, Matteo Fiorito, Marta Mottura, Giuseppe Visalli, Benedetto Vigna
  • Publication number: 20030109183
    Abstract: A process for bonding two distinct substrates that integrate microsystems, including the steps of forming micro-integrated devices in at least one of two substrates using micro-electronic processing techniques and bonding the substrates. Bonding is performed by forming on a first substrate bonding regions of deformable material and pressing the substrates one against another so as to deform the bonding regions and to cause them to react chemically with the second substrate. The bonding regions are preferably formed by a thick layer of a material chosen from among aluminum, copper and nickel, covered by a thin layer of a material chosen from between palladium and platinum. Spacing regions ensure exact spacing between the two wafers.
    Type: Application
    Filed: September 12, 2002
    Publication date: June 12, 2003
    Applicants: STMicroelectronics S.r.I., Hewlett-Packard Company
    Inventors: Ubaldo Mastromatteo, Mauro Bombonati, Daniela Morin, Marta Mottura, Mauro Marchi
  • Publication number: 20020127761
    Abstract: A process for manufacturing components in a multi-layer wafer, including the steps of: providing a multi-layer wafer comprising a first semiconductor material layer, a second semiconductor material layer (, and a dielectric material layer arranged between the first and the second semiconductor material layer; and removing the first semiconductor material layer initially by mechanically thinning the first semiconductor material layer, so as to form a residual conductive layer, and subsequently by chemically removing the residual conductive layer. In one application, the multi-layer wafer is bonded to a first wafer of semiconductor material, with the second semiconductor material layer facing the first wafer, after micro-electromechanical structures have been formed in the second semiconductor material layer of the multi-layer wafer.
    Type: Application
    Filed: December 19, 2001
    Publication date: September 12, 2002
    Applicant: STMicroelectronics S.r.I.
    Inventors: Marta Mottura, Alessandra Fischetti, Marco Ferrera, Bernardino Zerbini, Mauro Bombonati