Patents by Inventor Martin Aureliano Hassner
Martin Aureliano Hassner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7178086Abstract: Techniques for correcting data bytes on a data storage disk that have been rewritten are provided. A data storage system generates a long block membership (LBM) byte for each sector. The LBM bytes indicates whether the sector is part of a block of sectors. A data storage system can determine whether a failed sector is part of a long block. The data storage system adds the LBM contributions to the CRC and ECC bytes and then attempts to correct the failed sector. If the correction process is successful, the data storage system declares a miscorrection. If the error is not successfully corrected, the data storage system again adds the LBM contributions to the CRC and ECC bytes and then attempts to correct the failed sector. If the correction process is successful, the data correction is accepted if the error pattern and the check byte overlap is greater than a threshold.Type: GrantFiled: September 17, 2003Date of Patent: February 13, 2007Assignee: Hitachi Global Storage Technologies Netherlands, B.V.Inventors: Martin Aureliano Hassner, Vipul Srivastava, Nyles Heise
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Patent number: 7134066Abstract: The Hamming distance of an array of storage devices is increased by generating a parity check matrix based on column equations that are formed using an orthogonal parity code and includes a higher-order multiplier that changes each column. The higher order multiplier is selected to generate a finite basic field of a predetermined number of elements. The array has M rows and N columns, such that M is greater than or equal to three and N is greater than or equal to three. Row 1 through row M?2 of the array each have n–p data storage devices and p parity storage devices. Row M?1 of the array has n?(p+1) data storage devices and (p+1) parity storage devices. Lastly, row M of the array has N parity storage devices.Type: GrantFiled: October 20, 2003Date of Patent: November 7, 2006Assignee: International Business Machines CorporationInventors: Martin Aureliano Hassner, Steven R. Hetzler, Tetsuya Tamura, Barry Marshall Trager, Shmuel Winograd
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Patent number: 7131052Abstract: An error correction algebraic decoder and an associated method correct a combination of a B-byte burst of errors and t-byte random errors in a failed sector, by iteratively adding and removing an erasure (N?B) times until the entire failed sector has been scanned, provided the following inequality is satisfied: (B+2t)?(R?1), where N denotes the number of bytes, B denotes the length of the burst of errors, t denotes the total number of random errors, and R denotes the number of check bytes in the failed sector. This results in a corrected sector at a decoding latency that is a generally linear function of the number of the check bytes R, as follows: Decoding Latency=5R(N?B).Type: GrantFiled: August 12, 2002Date of Patent: October 31, 2006Assignee: International Business Machines CorporationInventors: Martin Aureliano Hassner, Tetsuya Tamura, Barry Marshall Trager, Shmuel Winograd
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Patent number: 7080200Abstract: In a disk drive that uses large block sizes (e.g., 4 KB) for storing data and that responds to read and write requests from a client that uses small block sizes (e.g., 512 bytes), at least the starting and ending 4K blocks of read data are cached. Since much disk data that is the subject of a write request is first read, upon a subsequent write request the drive controller determines whether the starting and ending blocks are in cache and if so, writes new data to those blocks, calculates a full ECC for them, and then calculates ECC for intervening blocks and writes new data to the intervening blocks. If both starting and ending blocks are not in cache the drive controller executes either a high data integrity routine or a high performance routine as chosen by the user.Type: GrantFiled: August 14, 2003Date of Patent: July 18, 2006Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Martin Aureliano Hassner, Richard M. H. New, Spencer W. Ng
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Patent number: 6928515Abstract: A system and associated method efficiently complete write commands in an ISF disk drive/RAID system with minimal disk accesses to the underlying disk drives. The system updates data in a parity-based disk array system by receiving a write command to write new data. The present system minimizes the number of disk accesses. The present system completes the same or comparable write commands in a total of four accesses to the disk drives. This is realized by combining the read-modify-write operation of updating one or more sectors in an ISF cluster with the read-modify-write operation associated with updating one or more sectors in a parity-based array system, such as a RAID-5 system.Type: GrantFiled: November 9, 2002Date of Patent: August 9, 2005Assignee: International Business Machines CorporationInventors: Martin Aureliano Hassner, Steven R. Hetzler, Spencer W. Ng
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Patent number: 6903887Abstract: A method and an apparatus encodes and decodes blocks having a predetermined number of sectors of data bytes to detect and correct data bytes in error in each sector of a block. The method and the apparatus generates sector level check bytes for each sector in the block responsive to the data bytes in each sector according to a first level of an error correction code, and generates block level check bytes for a predetermined sector in the block responsive to the sector level check bytes of various sectors, including the predetermined sector, according to at least a second level of the error correction code.Type: GrantFiled: January 3, 2002Date of Patent: June 7, 2005Assignee: International Business Machines CorporationInventors: Hideo Asano, Martin Aureliano Hassner, Nyles Norbert Heise, Tetsuya Tamura
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Patent number: 6891690Abstract: An encoding system and associated method protect against miscorrection due to parity sector correction in, for example, an on-drive RAID system. The system adds a parity cluster block, which itself is a complete, C3-protected cluster. Having the cluster level, C4 level correction, by parity sectors, checked and verified by C3 checks that have high reliability level, as well as the capability for checking consistency of a cluster block, even in the presence of “jami” errors, makes this possibility unlikely. A scrub algorithm avoids read-modify-write operations by deferring the completion of the C2 and C3-ckecks until the storage device is idle.Type: GrantFiled: November 20, 2002Date of Patent: May 10, 2005Assignee: International Business Machines CorporationInventors: Hideo Asano, Martin Aureliano Hassner, Nyles Norbert Heise, Steven R. Hetzler, Tetsuya Tamura
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Patent number: 6842062Abstract: An integrated electronic circuit includes a plurality of active circuits connected together in cascade. A feedback loop is between an output of a last active circuit and an input of a first active circuit so that the plurality of active devices function as a non-linear device, such as an inductor. The integrated electronic circuit may be integrated or used in association with a circuit network including other non-linear devices.Type: GrantFiled: August 9, 2002Date of Patent: January 11, 2005Assignees: STMicroelectronics S.r.l., International Business Machines CorporationInventors: Maurizio Zuffada, Giorgio Betti, Francesco Chrappan Soldavini, Martin Aureliano Hassner
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Publication number: 20040250196Abstract: An efficient method for finding all the possible corrections of a bust of length b and e random errors consists of finding a polynomial whose roots are the candidate location for l— the location of the beginning of the burst—thus avoiding the search over all possible values of l (it is assumed that the burst is non-trivial, i.e., at least one of its errors has a non-zero value). In order to reduce the number of spurious solutions, it is assumed that the number of syndromes is t=2e+b+s, where s is at least 2. The larger the value of s the less likely it is that the algorithm will generate “spurious” solutions. Once the location of the burst is known, standard procedures are used to determine the magnitudes of the burst errors and the location and magnitude of the random errors.Type: ApplicationFiled: June 4, 2003Publication date: December 9, 2004Inventors: Martin Aureliano Hassner, Barry Marshall Trager, Shmuel Winograd
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Patent number: 6792569Abstract: An error correction algebraic decoder uses a key equation solver for calculating the roots of finite field polynomial equations of degree up to six, and lends itself to efficient hardware implementation and low latency direction calculation. The decoder generally uses a two-step process. The first step is the conversion of quintic equations into sextic equations, and the second step is the adoption of an invertible Tschirnhausen transformation to reduce the sextic equations by eliminating the degree 5 term. The application of the Tschirnhausen transformation considerably decreases the complexity of the operations required in the transformation of the polynomial equation into a matrix. The second step defines a specific Gaussian elimination that separates the problem of solving quintic and sextic polynomial equations into a simpler problem of finding roots of a quadratic equation and a quartic equation.Type: GrantFiled: April 24, 2001Date of Patent: September 14, 2004Assignee: International Business Machines CorporationInventors: Charles Edwin Cox, Martin Aureliano Hassner, Barry Marshall Trager, Shmuel Winograd
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Patent number: 6777998Abstract: An integrated electronic circuit includes a plurality of active circuits connected together in cascade. A feedback loop is between an output of a last active circuit and an input of a first active circuit so that the plurality of active devices function as a non-linear device, such as a capacitor. The integrated electronic circuit may be integrated or used in association with a circuit network including other non-linear devices.Type: GrantFiled: August 9, 2002Date of Patent: August 17, 2004Assignees: STMicroelectronics S.r.l., International Business Machines CorporationInventors: Maurizio Zuffada, Giorgio Betti, Francesco Chrappan Soldavini, Martin Aureliano Hassner
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Publication number: 20040095666Abstract: An encoding system and associated method protect against miscorrection due to parity sector correction in, for example, an on-drive RAID system. The system adds a parity cluster block, which itself is a complete, C3-protected cluster. Having the cluster level, C4 level correction, by parity sectors, checked and verified by C3 checks that have high reliability level, as well as the capability for checking consistency of a cluster block, even in the presence of “jami” errors, makes this possibility unlikely. A scrub algorithm avoids read-modify-write operations by deferring the completion of the C2 and C3-ckecks until the storage device is idle.Type: ApplicationFiled: November 20, 2002Publication date: May 20, 2004Applicant: International Business Machines CorporationInventors: Hideo Asano, Martin Aureliano Hassner, Nyles Norbert Heise, Steven R. Hetzler, Tetsuya Tamura
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Publication number: 20040093464Abstract: A system and associated method efficiently complete write commands in an ISF disk drive/RAID system with minimal disk accesses to the underlying disk drives. The system updates data in a parity-based disk array system by receiving a write command to write new data. The present system minimizes the number of disk accesses. The present system completes the same or comparable write commands in a total of four accesses to the disk drives. This is realized by combining the read-modify-write operation of updating one or more sectors in an ISF cluster with the read-modify-write operation associated with updating one or more sectors in a parity-based array system, such as a RAID-5 system.Type: ApplicationFiled: November 9, 2002Publication date: May 13, 2004Applicant: International Business Machines CorporationInventors: Martin Aureliano Hassner, Steven R. Hetzler, Spencer W. Ng
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Publication number: 20040030737Abstract: An error correction algebraic decoder and an associated method correct a combination of a B-byte burst of errors and t-byte random errors in a failed sector, by iteratively adding and removing an erasure (N−B) times until the entire failed sector has been scanned, provided the following inequality is satisfied: (B+2t)≦(R−1), where N denotes the number of bytes, B denotes the length of the burst of errors, t denotes the total number of random errors, and R denotes the number of check bytes in the failed sector. This results in a corrected sector at a decoding latency that is a generally linear function of the number of the check bytes R, as follows: Decoding Latency=5R(N−B).Type: ApplicationFiled: August 12, 2002Publication date: February 12, 2004Applicant: International Business Machines CorporationInventors: Martin Aureliano Hassner, Tetsuya Tamura, Barry Marshall Trager, Shmuel Winograd
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Patent number: 6687067Abstract: A Hilbert transform is used to process perpendicular magnetic recording signals from both single layer and dual layer disks to produce a complex analytic signal. This complex analytic signal is used to derive angles of magnetization, which depend on the distance between recorded magnetic transitions and consequently which can be used in error estimation. Moreover, the Hilbert transform in cooperation with an equalizer FIR optimizes transformation of the signal such that conventional longitudinal recording processing methods can subsequently be used to process the signal that is read back from the magnetic recording medium.Type: GrantFiled: March 9, 2001Date of Patent: February 3, 2004Assignee: International Business Machines CorporationInventors: Francesco Brianti, Bertrand Gabillard, Martin Aureliano Hassner, Manfred Ernst Schabes, Yoshiaki Sonobe, Barry Marshall Trager
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Patent number: 6671850Abstract: An on-the-fly algebraic error correction system and corresponding method for reducing error location search are presented. The method transforms an error locator polynomial into two transformed polynomials whose roots are elements in a smaller subfield, in order to significantly simplify the complexity, and to reduce the latency of the error correcting system hardware implementation. More specifically, if the error locator polynomial is over a finite field of (22n) elements, the transformed polynomial is over a finite subfield of (2n) elements. Thus, the problem of locating the roots of the error locator polynomial is reduced to locating the roots of the transformed polynomials. Assuming the error locator polynomial is of degree m, the present method requires at most (m2/2) evaluations of polynomials over the Galois field GF(22n) and (2n+1) evaluations over the subfield GF(2n) or root finding of two polynomials of at most a degree m over the subfield GF(2n).Type: GrantFiled: May 1, 2000Date of Patent: December 30, 2003Assignee: International Business Machines CorporationInventors: Charles Edwin Cox, Martin Aureliano Hassner, Barry Marshall Trager, Shmuel Winograd
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Patent number: 6654924Abstract: A system and method for algebraically correcting errors in complex digitized phase signals from a magneto-resistive or giant magneto-resistive (MR/GMR) head readback waveform includes a data state machine that encodes phase symbols into data bits in accordance with, e.g., the (1, 10) constraint and a parity state machine that generates parity symbols such that a single inserted parity symbol does not violate the (1, 7) constraint in a run length limited code and furthermore the data following the insertion will not violate the (1, 10) constraint in a run length limited code. The state machines can be used as a trellis to perform maximum likelihood decoding on received coded data, thus performing soft algebraic error detection on received data. The invention thus guarantees better overall error rate performance than hard decision post processing of blocks of detected bits by a parity check matrix which is otherwise vulnerable to loss of bit synchronization at high linear density recording.Type: GrantFiled: September 29, 2000Date of Patent: November 25, 2003Assignee: International Business Machines CorporationInventors: Martin Aureliano Hassner, Francesco Rezzi, Barry Marshall Trager
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Patent number: 6651213Abstract: A method for adaptively controlling the error correction redundancy is presented. The method utilizes test information collected at the file characterization test to adaptively determine the quantity of error correction code bytes needed at a multitude of levels of the error correction scheme. The error correction needed at the sub-block level is determined from a measurement of the back ground noise floor. At the block level the file characterization is specific to zones identified by head, disk, sector and cylinder. The formatting efficiency of the drive is increased by adaptively linking the length of the error correction code to the location of the zone. By measuring the error rate (E/R) on a per zone basis and comparing this rate to the disk level E/R the ECC can be optimized on a per-zone basis.Type: GrantFiled: March 19, 2001Date of Patent: November 18, 2003Assignee: International Business Machines CorporationInventors: Martin Aureliano Hassner, Bernd Lamberts, Thomas Earl Stanley
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Publication number: 20030147167Abstract: A method and an apparatus encodes and decodes blocks having a predetermined number of sectors of data bytes to detect and correct data bytes in error in each sector of a block. The method and the apparatus generates sector level check bytes for each sector in the block responsive to the data bytes in each sector according to a first level of an error correction code, and generates block level check bytes for a predetermined sector in the block responsive to the sector level check bytes of various sectors, including the predetermined sector, according to at least a second level of the error correction code.Type: ApplicationFiled: January 3, 2002Publication date: August 7, 2003Applicant: International Business Machines CorporationInventors: Hideo Asano, Martin Aureliano Hassner, Nyles Norbert Heise, Tetsuya Tamura
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Patent number: 6553536Abstract: A soft error correction algebraic decoder and an associated method use erasure reliability numbers to derive error locations and values. More specifically, symbol reliability numbers from a maximum likelihood (ML) decoder as well as a parity check success/failure from inner modulation code symbols are combined by a Reed-Solomon decoder in an iterative manner, such that the ratio of erasures to errors is maximized. The soft error correction (ECC) algebraic decoder and associated method decode Reed Solomon codes using a binary code and detector side information. The Reed Solomon codes are optimally suited for use on erasure channels. A threshold adjustment algorithm qualifies candidate erasures based on a detector error filter output as well as modulation code constraint success/failure information, in particular parity check or failure as current modulation codes in disk drive applications use parity checks. This algorithm creates fixed erasure inputs to the Reed Solomon decoder.Type: GrantFiled: July 7, 2000Date of Patent: April 22, 2003Assignee: International Business Machines CorporationInventors: Martin Aureliano Hassner, Richard Michael Hamilton New, Arvind Motibhai Patel, Tetsuya Tamura, Barry Marshall Trager