Abstract: An integrated electronic circuit includes a plurality of active circuits connected together in cascade. A feedback loop is between an output of a last active circuit and an input of a first active circuit so that the plurality of active devices function as a non-linear device, such as a capacitor. The integrated electronic circuit may be integrated or used in association with a circuit network including other non-linear devices.

Abstract: An integrated electronic circuit includes a plurality of active circuits connected together in cascade. A feedback loop is between an output of a last active circuit and an input of a first active circuit so that the plurality of active devices function as a non-linear device, such as an inductor. The integrated electronic circuit may be integrated or used in association with a circuit network including other non-linear devices.

Abstract: A circuit combines a read signal from an MR/GMR read head with a signal generated by a matched filter, the parameters of which depend on the geometry of the head and the output of which, generated every Nth clock period, includes a real part and an imaginary part that models an expected head response. The combined signal is phase equalized and sent to a complex correlator, which integrates the signal over N clock periods to output a correlated signal having real and imaginary portions of the Nth root of unity which correspond to bits in an N-clock data unit. The real and imaginary portions can subsequently be digitized and analyzed for errors.

Abstract: A method for adaptively controlling the error correction redundancy is presented. The method utilizes test information collected at the file characterization test to adaptively determine the quantity of error correction code bytes needed at a multitude of levels of the error correction scheme. The error correction needed at the sub-block level is determined from a measurement of the back ground noise floor. At the block level the file characterization is specific to zones identified by head, disk, sector and cylinder. The formatting efficiency of the drive is increased by adaptively linking the length of the error correction code to the location of the zone. By measuring the error rate (E/R) on a per zone basis and comparing this rate to the disk level E/R the ECC can be optimized on a per-zone basis.

Abstract: An error correction algebraic decoder uses a key equation solver for calculating the roots of finite field polynomial equations of degree up to six, and lends itself to efficient hardware implementation and low latency direction calculation. The decoder generally uses a two-step process. The first step is the conversion of quintic equations into sextic equations, and the second step is the adoption of an invertible Tschirnhausen transformation to reduce the sextic equations by eliminating the degree 5 term. The application of the Tschirnhausen transformation considerably decreases the complexity of the operations required in the transformation of the polynomial equation into a matrix. The second step defines a specific Gaussian elimination that separates the problem of solving quintic and sextic polynomial equations into a simpler problem of finding roots of a quadratic equation and a quartic equation.

Abstract: A Hilbert transform is used to process perpendicular magnetic recording signals from both single layer and dual layer disks to produce a complex analytic signal. This complex analytic signal is used to derive angles of magnetization, which depend on the distance between recorded magnetic transitions and consequently which can be used in error estimation. Moreover, the Hilbert transform in cooperation with an equalizer FIR optimizes transformation of the signal such that conventional longitudinal recording processing methods can subsequently be used to process the signal that is read back from the magnetic recording medium.

Abstract: A method and apparatus for ensuring the integrity of data that can detect errors that remain when the data correction scheme fails to correct at least some of the errors, or has added additional errors. Reed-Solomon check symbols are used for error correction and cyclic redundancy check symbols are used to detect the remaining errors. The roots of the generator polynomials used to generate the Reed-Solomon check symbols and the cyclic redundancy check symbols meet a selected subset of a plurality of conditions. The roots are further selected so that the necessary exponentiation may be performed by a combination of exponentiations by powers of two and multiplications. The Reed-Solomon check symbols are generated based on the data portion of the data block. A deterministically altered data stream is generated based on the data portion of the data block and the cyclic redundancy check symbols are generated based on the deterministically altered data stream.

Abstract: A method and apparatus for ensuring the integrity of data that can detect errors that remain when the data correction scheme fails to correct at least some of the errors, or has added additional errors. Reed-Solomon check symbols are used for error correction and cyclic redundancy check symbols are used to detect the remaining errors. The roots of the generator polynomials used to generate the Reed-Solomon check symbols and the cyclic redundancy check symbols meet a selected subset of a plurality of conditions. The roots are further selected so that the necessary exponentiation may be performed by a combination of exponentiations by powers of two and multiplications. The Reed-Solomon check symbols are generated based on the data portion of the data block. A deterministically altered data stream is generated based on the data portion of the data block and the cyclic redundancy check symbols are generated based on the deterministically altered data stream.

Abstract: A composite encoder/syndrome generating device that both computes check symbols over counterpart data symbol strings to form codewords, and derives syndromes from codewords indicative of their error state. The multistage device provides recursive processing paths at each stage of depth corresponding to the number of symbols concurrently applied to the device. The device is adapted as an encoder when the feed-forward paths between stages are enabled; it is adapted as a syndrome generator upon their disablement. The number of symbols concurrently processed may be varied from clock cycle to clock cycle by conforming the recursion paths per stage to the number of symbols applied as input to the device.

Abstract: A computationally efficient, machine-implementable method and means for detecting and correcting errors in received codewords on-the-fly within the capacity of a linear cyclic code using ultra-fast error location processing. Each error locator polynomial of degree t over a finite Galois field derived from a codeword syndrome is mapped into a matrix representative of a system of linear simultaneous equations related to the polynomial coefficients. Roots indicative of error locations within the codeword are extracted from the matrix by a modified Gaussian Elimination process for all the roots where t≦5 and at least one root plus a subset of candidate roots from the finite field for iterative substitution where t>5. Corrected values are separately determined and correction is secured by logically combining the corrected values with the codeword values in error at the error locations represented by the roots.

Abstract: A method and means for enhancing the error detection and correction capability obtained when a plurality of data byte strings are encoded in a two-level, block-formatted linear code using code word and block-level redundancy. This is accomplished by vector multiplication of N data byte vectors and a nonsingular invertible integration matrix with nonzero minors with order up to B to secure the necessary interleaving among N data byte vectors to form modified data byte vectors. The selected patterns of interleaving ensure single-pass, two-level linear block error correction coding when the modified data vectors are applied to an ECC encoding arrangement. The method and means are parameterized so as to either extend or reduce the number of bursty codewords or subblocks to which the block-level check bytes can be applied.

Abstract: A generalized method for dynamically deriving configuration information from a set of given parameters for detecting binary-valued sequences from (d, k) partial-response (PR) coded waveforms of predetermined shape, for applying the derived information to configure a processor, and for operating the configured processor as a PR detector.

Abstract: A method and means for reducing high-duty-cycle unconstrained binary signal sequences in storage and communications processes and systems by invertibly mapping such sequences into a (1, k) rate ⅔ RLL codestream constrained to a duty cycle substantially approximating one-third. That is, binary sequences ordinarily mapping into high-duty-cycle RLL-code sequences are either inhibited from repeating indefinitely or excluded.

Abstract: A computationally efficient, machine-implementable method and means for detecting and correcting errors in received codewords on-the-fly within the capacity of a linear cyclic code using ultra-fast error location processing. Each error locator polynomial of degree t over a finite Galois field derived from a codeword syndrome is mapped into a matrix representative of a system of linear simultaneous equations related to the polynomial coefficients. Roots indicative of error locations within the codeword are extracted from the matrix by a modified Gaussian Elimination process for all the roots where t.ltoreq.5 and at least one root plus a subset of candidate roots from the finite field for iterative substitution where t>5. Corrected values are separately determined and correction is secured by logically combining the corrected values with the codeword values in error at the error locations represented by the roots.

Abstract: The invention relates to an arithmetic unit (AU) in combination with an algebraic block ECC decoder for controlling errors in an electronically recorded digital data message by performing at least one of a plurality of predetermined arithmetic operations on the data message in one or more of a plurality of subfields of a first GF(2.sup.12) or a second GF(2.sup.8) finite field. The arithmetic operations are selected either from a first group of operations associated with a first subfield GF(2.sup.4) as cubically extended to the first finite field GF(2.sup.12) or as quadratically extended to the second finite field GF(2.sup.8), or selected from a second group of operations associated with a second subfield GF(2.sup.6) as quadratically extended to the first finite field GF(2.sup.12).

Abstract: The present invention is a circuit for performing a computation of a plurality of coefficients of an error locator polynomial and a plurality of coefficients of an error evaluator polynomial in a system for correcting errors in a Reed-Solomon encoded datastream, comprising a syndrome generator outputting syndromes of the datastream. The circuit of the present invention is coupled to the syndrome generator and receives the syndromes.

Abstract: An efficient method and apparatus corrects synchronization problems in the recovery data stored on magnetic media. Resolving blocks are inserted into the unconstrained data string at specified intervals. A resolving block is constructed to do two things: reset the encoding automaton and produce in the constrained data string blocks which allow correction of synchronization. Before decoding, synchronization is corrected. The constrained data string is decoded, and then the resolving block removed. The blocks are inserted before run-length limited encoding occurs and deleted after run-length limited decoding takes place. The run-length limited encoder and decoder are unchanged.