Abstract: Embodiments of present invention provide a method of forming an extreme ultraviolet (EUV) mask. The method includes subliming a radiation-sensitive material onto a surface of an EUV blank substrate; exposing the radiation-sensitive material to an ionizing radiation to form an EUV mask pattern; and removing a portion of the radiation-sensitive material from the surface of the EUV blank substrate where the portion of the radiation-sensitive material is unexposed to the ionizing radiation. An EUV mask made therefrom, and the related radiation-sensitive material are also provided.

Abstract: To increase the efficiency of electronic design automation, employ a first subset of integrated circuit patterning modeling data to generate weights of a neural network-based patterning model; employ a second subset of integrated circuit patterning modeling data to generate updated weights of the neural network-based patterning model, to obtain an updated neural network-based patterning model; evaluate the updated neural network-based patterning model; and responsive to the evaluating of the updated neural network-based patterning model being successfully completed, deploy the updated neural network-based patterning model.

Abstract: According to one or more embodiments of the present invention a computer-implemented method for fabricating a chip includes generating, using an aerial image generation system, a set of aerial images for a chip layout, the set of aerial images including an aerial image corresponding to each region from the chip layout. The method further includes automatically determining, using an artificial neural network, a feature vector for each aerial image from the set of aerial images. The method further includes clustering the aerial images using their corresponding feature vectors. The method further includes selecting, as test samples, a predetermined number of aerial images from each cluster. The method further includes performing a pattern coverage inspection of the chip layout using the aerial images that are selected as test samples.

Abstract: The present invention relates to phosphorescent organic light-emitting diodes (OLEDs) including a hole-transporting or a hole-transporting and an electron-blocking layer including an N,N,N?,N?-tetraaryl-phenylene-3,5-diamine or an N,N,N?,N?-tetraaryl-1,1?-biphenyl-3,3?-diamine matrix compound and to new N,N,N?,N?-tetraarylsubstituted m-arylene diamine compounds useful as hole-transporting and electron-blocking layer matrices in phosphorescent OLEDs.

Abstract: A method for generating physical design layout patterns includes selecting as training data one or more physical design layout patterns of integrated multi-layers for features in at least two layers of a given patterned structure. The method also includes converting the physical design layout patterns into three-dimensional arrays, a given three-dimensional array comprising a set of two-dimensional arrays each representing features of one layer of the layers in a given one of the physical design layout patterns. The method further includes training, utilizing the three-dimensional arrays, a generative adversarial network (GAN) comprising a discriminator neural network and a generator neural network. The method further includes generating synthetic three-dimensional arrays utilizing the generator neural network of the trained GAN, a given synthetic three-dimensional array comprising a set of two-dimensional arrays each representing features for a new layer of a new physical design layout pattern.

Abstract: A method for generating physical design layout patterns includes selecting as training data a set of physical design layout patterns of features in a given layer of a given patterned structure and converting the physical design layout patterns into two-dimensional (2D) arrays comprising entries for different locations in the given layer of the given patterned structure with values representing presence of the features at the different locations. The method also includes training, utilizing the 2D arrays, a generative adversarial network (GAN) comprising a discriminator neural network and a generator neural network. The method further includes generating one or more synthetic 2D arrays utilizing the trained generator neural network of the GAN, a given synthetic 2D array comprising entries for different locations in the given layer of a new physical design layout pattern with values representing presence of the features at the different locations of the new physical design layout pattern.

Abstract: According to one or more embodiments of the present invention a computer-implemented method for fabricating a chip includes generating, using an aerial image generation system, a set of aerial images for a chip layout, the set of aerial images including an aerial image corresponding to each region from the chip layout. The method further includes automatically determining, using an artificial neural network, a feature vector for each aerial image from the set of aerial images. The method further includes clustering the aerial images using their corresponding feature vectors. The method further includes selecting, as test samples, a predetermined number of aerial images from each cluster. The method further includes performing a pattern coverage inspection of the chip layout using the aerial images that are selected as test samples.

Abstract: Methods and systems for fabricating an integrated circuit include training a machine learning model using a training set that includes known physical design layout patterns that are classified according to whether the patterns include a hotspot. It is determined whether an input physical design layout pattern includes a hotspot using the machine learning model. A hotspot localization is generated for the input physical design layout patterns. The input physical design pattern is adjusted to cure the hotspot. A circuit is fabricated in accordance with the adjusted input physical design layout pattern.

Abstract: A method for generating physical design layout patterns includes selecting as training data a set of physical design layout patterns of patterned structures. The method also includes training, utilizing physical design layout patterns containing hotspots, a first neural network model configured to generate synthetic physical design layout patterns, and training, utilizing physical design layout patterns that do and do not contain hotspots, a second neural network model configured to classify whether physical design layout patterns contain hotspots. The method further includes generating synthetic physical design layout patterns containing hotspots by utilizing the trained first neural network model to generate synthetic physical design layout patterns and utilizing the trained second neural network model to select the synthetic physical design layout patterns containing hotspots.

Abstract: Methods and systems for fabricating an integrated circuit include training a machine learning model using a training set that includes known physical design layout patterns that are classified according to whether the patterns include a hotspot. It is determined whether an input physical design layout pattern includes a hotspot using the machine learning model. A hotspot localization is generated for the input physical design layout patterns. The input physical design pattern is adjusted to cure the hotspot. A circuit is fabricated in accordance with the adjusted input physical design layout pattern.

Abstract: A method for generating physical design layout patterns includes selecting as training data a set of physical design layout patterns of features in a given layer of a given patterned structure and converting the physical design layout patterns into two-dimensional (2D) arrays comprising entries for different locations in the given layer of the given patterned structure with values representing presence of the features at the different locations. The method also includes training, utilizing the 2D arrays, a generative adversarial network (GAN) comprising a discriminator neural network and a generator neural network. The method further includes generating one or more synthetic 2D arrays utilizing the trained generator neural network of the GAN, a given synthetic 2D array comprising entries for different locations in the given layer of a new physical design layout pattern with values representing presence of the features at the different locations of the new physical design layout pattern.

Abstract: A method for generating physical design layout patterns of integrated multi-layers includes selecting as training data one or more physical design layout patterns of integrated multi-layers for features in at least two layers of a given patterned structure. The method also includes converting the physical design layout patterns into three-dimensional arrays, a given three-dimensional array comprising a set of two-dimensional arrays each representing features of one of the layers in a given physical design layout pattern. The method further includes training, utilizing the three-dimensional arrays, a generative adversarial network (GAN) comprising a discriminator neural network and a generator neural network.

Abstract: The present invention relates to phosphorescent organic light-emitting diodes (OLEDs) including a hole-transporting or a hole-transporting and an electron-blocking layer including an N,N,N?,N?-tetraaryl-phenylene-3,5-diamine or an N,N,N?,N?-tetraaryl-1,1?-biphenyl-3,3?-diamine matrix compound and to new N,N,N?,N?-tetraarylsubstituted m-arylene diamine compounds useful as hole-transporting and electron-blocking layer matrices in phosphorescent OLEDs.

Abstract: The present invention relates to phosphorescent organic light-emitting diodes (OLEDs) comprising a hole-transporting or a hole-transporting and an electron-blocking layer comprising an N,N,N?,N?-tetraaryl-phenylene-3,5-diamine or an N,N,N?,N?-tetraaryl-1,1?-biphenyl-3,3?-diamine matrix compound and to new N,N,N?,N?-tetraarylsubstituted m-arylene diamine compounds useful as hole-transporting and electron-blocking layer matrices in phosphorescent OLEDs.

Abstract: Obtaining optimal focus for exposing a photoresist in an EUV lithography with an EUV mask containing a pattern with an assist feature is disclosed. The EUV mask contains a repeating pattern, wherein the repeating pattern has two different pitches, i.e. a first pitch and a second pitch, and contains an assist feature between main features. Because the two different pitches have different focus offsets, the difference between linewidths of said gratings provides a calibration curve which is a measure of focus. The method for monitoring focus is performing a EUV exposure using a focus position with a pre-determined focus position as calibrated using the linewidth difference between the two gratings. The EUV mask for monitoring focus of present invention is applicable to both test and product masks.

Abstract: Obtaining optimal focus for exposing a photoresist in an EUV lithography with an EUV mask containing a pattern with an assist feature is disclosed. The EUV mask contains a repeating pattern, wherein the repeating pattern has two different pitches, i.e. a first pitch and a second pitch, and contains an assist feature between main features. Because the two different pitches have different focus offsets, the difference between linewidths of said gratings provides a calibration curve which is a measure of focus. The method for monitoring focus is performing a EUV exposure using a focus position with a pre-determined focus position as calibrated using the linewidth difference between the two gratings. The EUV mask for monitoring focus of present invention is applicable to both test and product masks.

Abstract: Obtaining optimal focus for exposing a photoresist in an EUV lithography with an EUV mask containing a pattern with an assist feature is disclosed. The EUV mask contains a repeating pattern, wherein the repeating pattern has two different pitches, i.e. a first pitch and a second pitch, and contains an assist feature between main features. Because the two different pitches have different focus offsets, the difference between linewidths of said gratings provides a calibration curve which is a measure of focus. The method for monitoring focus is performing a EUV exposure using a focus position with a pre-determined focus position as calibrated using the linewidth difference between the two gratings. The EUV mask for monitoring focus of present invention is applicable to both test and product masks.

Abstract: Obtaining optimal focus for exposing a photoresist in an EUV lithography with an EUV mask containing a pattern with an assist feature is disclosed. The EUV mask contains a repeating pattern, wherein the repeating pattern has two different pitches, i.e. a first pitch and a second pitch, and contains an assist feature between main features. Because the two different pitches have different focus offsets, the difference between linewidths of said gratings provides a calibration curve which is a measure of focus. The method for monitoring focus is performing a EUV exposure using a focus position with a pre-determined focus position as calibrated using the linewidth difference between the two gratings. The EUV mask for monitoring focus of present invention is applicable to both test and product masks.

Abstract: The present invention relates to organic light-emitting diodes (OLEDs) comprising at least one substantially organic layer comprising 1,N,N,N?,N?-pentakis(1,1?-biphenyl-4-yl)-phenylene-3,5-diamine matrix compound and to new 1,N,N,N?,N?-pentakis(1,1?-bi-phenyl-4-yl)-phenylene-3,5-diamine compound useful especially as hole-transporting and/or electron-blocking layer matrix in OLEDs.

Abstract: This invention relates to a method of obtaining optimal focus for exposing a photoresist in an EUV lithography with an EUV mask containing a pattern with an assist feature. The invention also relates to an EUV mask with a special focus test target for monitoring focus in EUV lithography, and a method of fabricating this EUV mask by designing the special focus test target. The EUV mask contains a repeating pattern, wherein the repeating pattern has two different pitches, i.e. a first pitch and a second pitch, and contains an assist feature between main features. Because the two different pitches have different focus offsets, the difference between linewidths of said gratings provides a calibration curve which is a measure of focus. The method for monitoring focus is performing an EUV exposure using a focus position with a pre-determined focus position as calibrated using the linewidth difference between the two gratings.