Abstract: A trench for isolating active devices on a semiconductor substrate, formed by creating a trench which has a peripheral edge, and disposing an isolating material in the trench. The isolating material extends over the peripheral edge of the trench, thereby covering at least a portion of the substrate surrounding the trench, and substantially limiting leakage of the active devices disposed on the substrate.

Abstract: An electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

Abstract: A trench for isolating active devices on a semiconductor substrate, formed by creating a trench which has a peripheral edge, and disposing an isolating material in the trench. The isolating material extends over the peripheral edge of the trench, thereby covering at least a portion of the substrate surrounding the trench, and substantially limiting leakage of the active devices disposed on the substrate.

Abstract: A trench for isolating active devices on a semiconductor substrate, formed by creating a trench which has a peripheral edge, and disposing an isolating material in the trench. The isolating material extends over the peripheral edge of the trench, thereby covering at least a portion of the substrate surrounding the trench, and substantially limiting leakage of the active devices disposed on the substrate.

Abstract: A semiconductor processing method of forming a resistor from semiconductive material includes: a) providing a node to which electrical connection to a resistor is to be made; b) providing a first electrically insulative material outwardly of the node; c) providing an exposed vertical sidewall in the first electrically insulative material outwardly of the node; d) providing a second electrically insulative material outwardly of the first material and over the first material vertical sidewall, the first and second materials being selectively etchable relative to one another; e) anisotropically etching the second material selectively relative to the first material to form a substantially vertically extending sidewall spacer over the first material vertical sidewall and to outwardly expose the first material adjacent the sidewall spacer, the spacer having an inner surface and an outer surface; f) etching the first material selectively relative to the second material to outwardly expose at least a portion of the s

Abstract: A trench for isolating active devices on a semiconductor substrate, formed by creating a trench which has a peripheral edge, and disposing an isolating material in the trench. The isolating material extends over the peripheral edge of the trench, thereby covering at least a portion of the substrate surrounding the trench, and substantially limiting leakage of the active devices disposed on the substrate.

Abstract: A well in a semiconductor wafer is partially filled by a tungsten plug having an irregular surface. There is an aluminum line exterior of the well for electrically connecting the tungsten plug into an electrical circuit. A doped polysilicon fillet having an irregular surface meshing with the irregular surface of the tungsten plug fills the portion of the well between the plug and line, making a reproducible good electrical connection between the tungsten plug and the aluminum line. The poly fillet is formed by a poly deposit and planarization performed between a tungsten plug overetch and aluminum line deposition.

Abstract: The present invention is a Static Random Access Memory fabrication process for forming a buried contact, by the steps of: patterning a photoresist layer over the field silicon dioxide regions and the spaced apart areas of the substrate, thereby providing a buried contact implant window to expose a portion of at least one spaced apart area and an adjacent field silicon dioxide end portion; implanting an N-type dopant through the buried implant contact window, the implant forming a first N-type diffusion region in the exposed spaced apart area and changing the etch rate of the exposed field silicon dioxide end portion; stripping the masking layer; growing a sacrificial silicon dioxide layer, over the field silicon dioxide regions and the spaced apart areas of the supporting silicon substrate, thereby annealing the exposed field silicon dioxide end portion and returning the etch rate of the exposed field silicon dioxide end portion to substantially the same etch rate as prior to the implantation step; stripping

Abstract: A method of providing electrical contact between a gate of a transistor device and an active area remote of the transistor device includes: a) providing a first layer of a conductivity capable material over a gate insulative layer; b) etching the first layer and gate layer to expose a contact area; c) providing a second layer of a second material over the contact area and first layer; d) etching the second layer selectively relative to the first material and the substrate to provide a pair of buried contact spacers over respective opposing edges of the first layer in the contact area, and to reexpose a portion of the contact area and the first layer; e) providing a third layer of a conductivity capable material over the first layer, the buried contact spacers and the exposed portion of the contact area; f) etching the first and third layers to define a transistor gate of one device and a transistor gate of another device, and to interconnect the transistor gate of the another device to the portion of the cont

Abstract: A semiconductor device isolation method of forming a channel stop in a semiconductor wafer comprises: a) selectively forming field oxide on a semiconductor wafer surface, the field oxide having a bird's beak region and a non-bird's beak region, the bird's beak region laterally extending into a desired region on the wafer; b) masking the bird's beak region and desired region; c) with the masking in place, ion implanting a selected material into the wafer through the non-bird's beak region of the field oxide to define a channel stop implant in the wafer under the non-bird's beak region of the field oxide, such non-bird's beak region implant being conducted at an implant angle along the bird's beak which is less than about 10.degree.

Abstract: A method of providing electrical contact between a gate of a transistor device and an active area remote of the transistor device includes: a) providing a first layer of a conductivity capable material over a gate insulative layer; b) etching the first and gate layers to expose a contact area; c) providing a second layer of a second material over the contact area and first layer; d) etching the second layer selectively relative to the first material and the substrate to provide a pair of buried contact spacers over respective opposing edges of the first layer in the contact area, and to reexpose a portion of the contact area and the first layer; e) providing a third layer of a conductivity capable material over the first layer, the buried contact spacers and the exposed portion of the contact area; f) etching the first and third layers to define a transistor gate of one device and a transistor gate of another device, and to interconnect the transistor gate of the another device to the portion of the contact a

Abstract: A buried contact between the gate of a transistor device formed at the surface of a semiconductor substrate and a diffusion region formed in the surface of the substrate remote from the transistor device. The buried contact includes a polysilicon interconnect structure formed after shaping of the gate layer and the gate insulator. The polysilicon interconnect structure engages a side edge and an adjoining lower surface of the gate layer at a location where the gate insulator has been removed by isotropic etching from between the gate layer and the surface of the substrate. The polysilicon interconnect layer also contacts the surface of the substrate beneath an overhanging edge of the gate layer so as to form a surface current pathway interface. Below the surface current pathway interface a migration region is formed by heat-induced movement of ions from the gate layer through the polysilicon interconnect structure.

Abstract: Methods for reducing encroachment of the field oxide into the active area on a silicon integrated circuit are disclosed. The present invention modifies the conventional LOCOS technique for forming active areas and field oxide areas on a silicon substrate. Rather than fully forming the field oxide regions immediately after the silicon nitride layer is patterned and etched on the substrate, a thin field oxide is grown. This oxide is partially wet etched to leave a ribbon of bare silicon around and extending under the edges of the silicon nitride mask. An additional nitride layer is deposited over the entire wafer and anisotropically etched to form a nitride spacer between the original nitride mask and the partially grown field oxide. The nitride spacer seals the edge of the active area by inhibiting the diffusion of oxygen under the nitride mask. During subsequent field oxidation, the nitride spacer greatly reduces the encroachment of the field oxide into the active area.

Abstract: A buried contact between the gate of a transistor device formed at the surface of a semiconductor substrate and a diffusion region formed in the surface of the substrate remote from the transistor device. The buried contact includes a polysilicon interconnect structure formed after shaping of the gate layer and the gate insulator. The polysilicon interconnect structure engages a side edge and an adjoining lower surface of the gate layer at a location where the gate insulator has been removed by isotropic etching from between the gate layer and the surface of the substrate. The polysilicon interconnect layer also contacts the surface of the substrate beneath an overhanging edge of the gate layer so as to form a surface current pathway interface. Below the surface current pathway interface a migration region is formed by heat-induced movement of ions from the gate layer through the polysilicon interconnect structure.

Abstract: A process for forming within a masking layer a self-aligned annular opening having a width that is substantially narrower than the space width that can be created directly using the maximum resolution of available photolithography. The process involves the following steps: creation of a mask island using conventional photomasking and etching techniques, the perimeter of said island defining the inner perimeter of the perimetric annular opening; blanket deposition of a spacer layer, the thickness of which is equal to the desired width of the annular opening; a blanket deposition of a thick protective layer that is independently etchable over the spacer layer; planarization of the protection layer to or below the top of the spacer layer; and isotropically etching the exposed spacer layer to form a narrow annular opening exposing the substrate. At this point the exposed substrate may be trenched in order to isolate the area definedd by the island, or it may be fabricated in some other configuration.