Abstract: Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer overlying the buried oxide layer, as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these materials. Other embodiments are described and claimed.

Abstract: A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si1-xGex. The highest layer may be of the form Si1-yGey on the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form Si1-zGez on the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.

Abstract: Techniques associated with providing multiple gate insulator thickness for a semiconductor device are generally described. In one example, an apparatus includes a semiconductor fin having an impurity introduced to at least a first side of the fin, a first oxide having a first thickness coupled with the first side of the fin, and a second oxide having a second thickness coupled with a second side of the fin, the second thickness being different from the first thickness as a result of the impurity introduced to the first side of the fin.

Abstract: Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer overlying the buried oxide layer, as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these materials. Other embodiments are described and claimed.

Abstract: A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si1-xGex. The highest layer may be of the form Si1-yGey on the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form Si1-zGez on the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.

Abstract: A method including forming a device on a substrate, the device including a gate electrode on a surface of the substrate; a first junction region and a second junction region in the substrate adjacent the gate electrode; and depositing a straining layer on the gate electrode.

Abstract: Method and structure to decrease area capacitance within a buried insulator device structure are disclosed. A portion of the substrate layer of a buried insulator structure opposite the insulator layer from the gate is doped with the same doping polarity as the source and drain regions of the device, to provide reduced area capacitance. Such doping may be limited to portions of the substrate which are not below the gate.

Abstract: There is disclosed an apparatus including a substrate defining an interior of the apparatus, a device exterior to the substrate including a gate electrode, and a straining layer exterior to the gate electrode and exterior to the substrate.

Abstract: Method to form a structure to decrease area capacitance within a buried insulator device structure is disclosed. A portion of the substrate layer of a buried insulator structure opposite the insulator layer from the gate is doped with the same doping polarity as the source and drain regions of the device, to provide reduced area capacitance. Such doping may be limited to portions of the substrate which are not below the gate.

Abstract: There is disclosed an apparatus including a substrate defining an interior of the apparatus, a device exterior to the substrate including a gate electrode, and a straining layer exterior to the gate electrode and exterior to the substrate.

Abstract: Method and structure to decrease area capacitance within a buried insulator device structure are disclosed. A portion of the substrate layer of a buried insulator structure opposite the insulator layer from the gate is doped with the same doping polarity as the source and drain regions of the device, to provide reduced area capacitance. Such doping may be limited to portions of the substrate which are not below the gate.