Abstract: A controller for a power converter, a corresponding power converter and a corresponding method are provided. The controller for a power converter includes a rectifier configured to receive an alternating current input signal and output rectified half waves, an output capacitor and a current control device is coupled between the rectifier and the output capacitor. After reaching a first maximum voltage, power flowing is gradually reduced, and later the current provided to the output capacitor is gradually ramped up.

Abstract: A method for operating a switch in a power converter, a drive circuit for operating a switch in a power converter, and a power converter are disclosed. The method includes: driving an electronic switch coupled to an inductor in a power converter based on a feedback signal (SFB) and a crossing detection voltage, wherein the feedback signal is dependent on an output parameter of the power converter and the crossing detection voltage is dependent on a voltage across an auxiliary winding coupled to the inductor; clamping the crossing detection voltage; monitoring an auxiliary current (IAUX) associated with clamping the crossing detection voltage; and detecting an overvoltage when the monitored current reaches a predefined threshold.

Abstract: A method and a control circuit for driving an electronic switch coupled to an inductor in a power converter in successive drive cycles each including an on-time and an off-time are disclosed. Driving the electronic switch includes: measuring an inductor voltage during the on-time in a drive cycle in order to obtain a first measurement value; measuring the inductor voltage during the off-time in a drive cycle in order to obtain a second measurement value; obtaining a first voltage measurement signal that is dependent on a sum of the first measurement value and the second measurement value; and adjusting the on-time in a successive drive cycle dependent on a feedback signal and the first voltage measurement signal.

Abstract: A method for driving an electronic switch in a power converter and a power converter are disclosed. The method includes: driving an electronic switch (1) coupled to an inductor (2) in the power converter, wherein driving the electronic switch (1) includes driving the electronic switch (1) in a plurality of drive cycles by a drive signal (SDRV), Driving the electronic switch (1) in at least one of the plurality of drive cycles includes: determining a desired duration (TON_DES) of a current (I1) through the switch (1); and adjusting a duration (TDRV) of an on-level of the drive signal (SDRV) dependent on the desired duration (TON_DES) and a delay time (TDEL) obtained in a preceding drive cycle. The delay time (TDEL) is a time duration, in the preceding drive cycle, between a first time instance (t1) when the drive signal (SDRV) changes from the on-level to an off-level and a second time instance (t2) when a current through the electronic switch (1) falls below a predefined threshold.

Abstract: A method for operating an electronic switch in a power converter and a control circuit for operating an electronic switch in a power converter are disclosed. The method includes: driving an electronic switch coupled to an inductor in a power converter in successive drive cycles each including an on-time and an off-time, wherein the off-time includes a demagnetization time period in which the inductor is demagnetized and a delay time, and wherein an end of the delay time is dependent on the occurrence of a predefined number of signal pulses of a pulse signal. The pulse signal includes a first portion that represents local minima of a voltage across the switch and, a second portion that includes signal pulses obtained by timely extrapolating the pulse signal of the first portion.

Abstract: A method and a control circuit for driving an electronic switch coupled to an inductor in a power converter in successive drive cycles each including an on-time and an off-time are disclosed. Driving the electronic switch includes: measuring an inductor voltage during the on-time in a drive cycle in order to obtain a first measurement value; measuring the inductor voltage during the off-time in a drive cycle in order to obtain a second measurement value; obtaining a first voltage measurement signal that is dependent on a sum of the first measurement value and the second measurement value; and adjusting the on-time in a successive drive cycle dependent on a feedback signal and the first voltage measurement signal.

Abstract: A method and a control circuit for driving an electronic switch coupled to an inductor in a power converter in successive drive cycles each including an on-time and an off-time are disclosed. Driving the electronic switch includes: measuring an inductor voltage during the on-time in a drive cycle in order to obtain a first measurement value; measuring the inductor voltage during the off-time in a drive cycle in order to obtain a second measurement value; obtaining a first voltage measurement signal that is dependent on a sum of the first measurement value and the second measurement value; and adjusting the on-time in a successive drive cycle dependent on a feedback signal and the first voltage measurement signal.

Abstract: A method for operating a switch in a power converter, a drive circuit for operating a switch in a power converter, and a power converter are disclosed. The method includes: driving an electronic switch coupled to an inductor in a power converter based on a feedback signal (SFB) and a crossing detection voltage, wherein the feedback signal is dependent on an output parameter of the power converter and the crossing detection voltage is dependent on a voltage across an auxiliary winding coupled to the inductor; clamping the crossing detection voltage; monitoring an auxiliary current (IAUX) associated with clamping the crossing detection voltage; and detecting an overvoltage when the monitored current reaches a predefined threshold.

Abstract: A power supply circuit is equipped with a converter circuit configured to convert an alternating current signal applied at an input of the power supply circuit into a direct current signal. A control circuit for the power supply circuit is configured to detect a phase of the alternating current signal and to control discharging of an internal capacitive element of the power supply circuit based on the detected phase of the alternating current signal.

Abstract: The techniques of this disclosure may digitally generate a driver signal with a period (or frequency) at a finer resolution than can be achieved by simply counting clock cycles of a system clock. The driver signal may be configured to trigger based on single output clock signal that may be phase-shifted relative to the master system clock. A clock phase shift circuit may increment the phase shift of the output clock signal to any fraction relative to the master system clock. A driver signal generated based on the phase-shifted output clock may achieve the high resolution in frequency desirable when controlling some pulse-width modulated circuits, such as an LLC converter.

Abstract: In some examples, a controller device is configured to control power electronics circuitry and includes a high-voltage (HV) pin, a power supply (VCC) pin, a startup device configured to conduct electricity from the HV pin to the VCC pin, and comparator circuitry configured to determine whether a voltage level of the VCC pin is greater than a turn-on voltage threshold. In some examples, the comparator circuitry is further configured to cause the controller device to enter a normal-operation mode in response to determining that the voltage level of the VCC pin is greater than the turn-on voltage threshold. In some examples, the controller device also includes level detection circuitry configured to determine the turn-on voltage threshold based on a level of the HV pin.

Abstract: A power supply circuit is equipped with a converter circuit configured to convert an alternating current signal applied at an input of the power supply circuit into a direct current signal. A control circuit for the power supply circuit is configured to detect a phase of the alternating current signal and to control discharging of an internal capacitive element of the power supply circuit based on the detected phase of the alternating current signal.

Abstract: In some examples, a controller device is configured to control power electronics circuitry and includes a high-voltage (HV) pin, a power supply (VCC) pin, a startup device configured to conduct electricity from the HV pin to the VCC pin, and comparator circuitry configured to determine whether a voltage level of the VCC pin is greater than a turn-on voltage threshold. In some examples, the comparator circuitry is further configured to cause the controller device to enter a normal-operation mode in response to determining that the voltage level of the VCC pin is greater than the turn-on voltage threshold. In some examples, the controller device also includes level detection circuitry configured to determine the turn-on voltage threshold based on a level of the HV pin.

Abstract: Techniques are disclosed for a level shifter configured to adjust current flow in response to measured current fluctuations due to common mode noise in the level shifter. For example, the level shifter includes a low-side control circuit configured to adjust a first current flowing into a first low-side terminal of an active high voltage level shifter device in response to a difference between the first low-side current and a second low-side current flowing into a second low-side terminal of an inactive high voltage level shifter device. The level shifter further includes a high-side receiver circuit configured to detect a difference between a first high-side current flowing into a first high-side terminal of the active high voltage level shifter device and a second high-side current flowing into a second high-side terminal of the inactive high voltage level shifter device.

Abstract: Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

Abstract: In some examples, a method of controlling a first switch and a second switch of a resonant mode power converter circuit, the method comprising delivering control signals to the first switch and the second switch at a switching frequency. The method also comprises determining, for a first driving period, a first phase relation between a phase of a resonant current in the resonant mode power converter circuit and a phase of the control signals. The method further comprises determining, for a second driving period, a second phase relation between a phase of the resonant current and a phase of the control signals, and controlling the switching frequency based on a difference of the first phase relation and the second phase relation.

Abstract: In some examples, a method of controlling a first switch and a second switch of a resonant mode power converter circuit, the method comprising delivering control signals to the first switch and the second switch at a switching frequency. The method also comprises determining, for a first driving period, a first phase relation between a phase of a resonant current in the resonant mode power converter circuit and a phase of the control signals. The method further comprises determining, for a second driving period, a second phase relation between a phase of the resonant current and a phase of the control signals, and controlling the switching frequency based on a difference of the first phase relation and the second phase relation.

Abstract: The techniques of this disclosure may digitally generate a driver signal with a period (or frequency) at a finer resolution than can be achieved by simply counting clock cycles of a system clock. The driver signal may be configured to trigger based on single output clock signal that may be phase-shifted relative to the master system clock. A clock phase shift circuit may increment the phase shift of the output clock signal to any fraction relative to the master system clock. A driver signal generated based on the phase-shifted output clock may achieve the high resolution in frequency desirable when controlling some pulse-width modulated circuits, such as an LLC converter.

Abstract: Techniques are disclosed for a level shifter configured to adjust current flow in response to measured current fluctuations due to common mode noise in the level shifter. For example, the level shifter includes a low-side control circuit configured to adjust a first current flowing into a first low-side terminal of an active high voltage level shifter device in response to a difference between the first low-side current and a second low-side current flowing into a second low-side terminal of an inactive high voltage level shifter device. The level shifter further includes a high-side receiver circuit configured to detect a difference between a first high-side current flowing into a first high-side terminal of the active high voltage level shifter device and a second high-side current flowing into a second high-side terminal of the inactive high voltage level shifter device.

Abstract: The techniques of this disclosure may digitally generate a driver signal with a period (or frequency) at a finer resolution than can be achieved by simply counting clock cycles of a system clock. The driver signal may be configured to trigger based on single output clock signal that may be phase-shifted relative to the master system clock. A clock phase shift circuit may increment the phase shift of the output clock signal to any fraction relative to the master system clock. A driver signal generated based on the phase-shifted output clock may achieve the high resolution in frequency desirable when controlling some pulse-width modulated circuits, such as an LLC converter.