Abstract: A method for treating urinary stress incontinence. The method includes non-invasively cooling target tissue during a first cooling step, a non-cooling step, and non-invasively cooling the target tissue in a second cooling step. The first cooling step, the non-cooling step, and the second cooling step are performed at predetermined temperatures for a predetermined period of time.

Abstract: One or more embodiments relate to a semiconductor structure, comprising: a conductive feature; an outer guard ring; and an inner guard ring between the outer guard ring and the conductive feature, the inner guard ring being electrically coupled to the conductive feature.

Abstract: A signal transmission arrangement is disclosed. A voltage converter includes a signal transmission arrangement.

Abstract: One or more embodiments relate to a semiconductor structure, comprising: a conductive feature; an outer guard ring; and an inner guard ring between the outer guard ring and the conductive feature, the inner guard ring being electrically coupled to the conductive feature.

Abstract: One or more embodiments relate to a semiconductor structure, comprising: a conductive feature; an outer guard ring; and an inner guard ring between the outer guard ring and the conductive feature, the inner guard ring being electrically coupled to the conductive feature.

Abstract: A signal transmission arrangement is disclosed. A voltage converter includes a signal transmission arrangement.

Abstract: A signal transmission arrangement is disclosed. A voltage converter includes a signal transmission arrangement.

Abstract: Techniques disclosed herein stress a dielectric layer until a pre-catastrophic, stress induced leakage current (SILC) condition is detected. When the pre-catastrophic SILC condition is detected, the stress is removed to prevent catastrophic failure of the dielectric and its associated device. Because these techniques prevent catastrophic failure of the dielectric layer, engineers can carry out physical failure analysis of the device, which is now known to have some type of defect due to detection of the pre-catastrophic SILC condition. In this way, the techniques disclosed herein allow engineers to more quickly determine an underlying cause of a defect so that yields can be kept at optimal levels.

Abstract: One or more embodiments related to a semiconductor structure, comprising: a conductive feature; an outer guard ring; and an inner guard ring between the outer guard ring and the conductive feature, the inner guard ring being electrically coupled to the conductive feature.

Abstract: An implant includes a humidity sensor for generating a signal indicative of humidity within the implant. A controller within the implant receives the signal indicative of humidity, and controls the implant based on the signal indicative of humidity.

Abstract: High voltage semiconductor devices and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming first trenches in an insulating material. A trap region is formed in the insulating material by introducing an impurity into the first trenches. The first trenches are filled with a conductive material.

Abstract: One or more embodiments related to a semiconductor structure, comprising: a conductive feature; an outer guard ring; and an inner guard ring between the outer guard ring and the conductive feature, the inner guard ring being electrically coupled to the conductive feature.

Abstract: Techniques disclosed herein stress a dielectric layer until a pre-catastrophic, stress induced leakage current (SILC) condition is detected. When the pre-catastrophic SILC condition is detected, the stress is removed to prevent catastrophic failure of the dielectric and its associated device. Because these techniques prevent catastrophic failure of the dielectric layer, engineers can carry out physical failure analysis of the device, which is now known to have some type of defect due to detection of the pre-catastrophic SILC condition. In this way, the techniques disclosed herein allow engineers to more quickly determine an underlying cause of a defect so that yields can be kept at optimal levels.

Abstract: High voltage semiconductor devices and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming first trenches in an insulating material. A trap region is formed in the insulating material by introducing an impurity into the first trenches. The first trenches are filled with a conductive material.

Abstract: A signal processing arrangement for a cochlear implant system is described. A sensing microphone senses an acoustic signal to generate a corresponding electrical sound signal. An information detection circuit performs spectral analysis on the sound signal to identify the presence of speech information. A sound signal processing circuit generates an implant communications signal for the cochlear implant system based on the sound signal, and has an energy saving operational mode wherein the implant communications signal is generated only when the information detection circuit identifies that speech information is present in the sound signal.

Abstract: A signal transmission arrangement is disclosed. A voltage converter includes a signal transmission arrangement.

Abstract: In one embodiment, an integrated circuit includes a memory array having a plurality of capacitors for storing data of an initial state in the memory array in an initial state. The integrated circuit also includes circuitry for occasionally inverting the data stored by the plurality of capacitors and tracking whether the current state of the data stored by the plurality of capacitors corresponds to the initial state. The circuitry inverts the data read out of the memory array during a read operation when the current state of the data does not correspond to the initial state.

Abstract: A system including a tester configured to measure a first current from a first die of neighboring dice and a second current from a second die of the neighboring dice. The tester is configured to compare the first current to the second current to detect damage in the neighboring dice.

Abstract: The invention relates to a method for arranging chips of a first substrate on a second substrate, in which the chips are grouped at least into first chips and into second chips, the first chips of the first substrate are singulated and the singulated first chips are arranged on the second substrate in such a way that each of the first chips on the second substrate is unambiguously assigned to the associated first chip on the first substrate.

Abstract: A method eliminates effects of defects on wafers caused by cavities adjacent to the surface of a semiconductor (e.g., silicon) wafer. A first insulating layer is applied to the surface of the semiconductor wafer and into the cavities adjacent to the surface. The applied first insulating layer is covered with a sacrificial layer. A selective back-etching of the sacrificial layer is carried out, such that the cavities adjacent to the surface remain filled with the sacrificial layer. A second insulating layer is applied directly to the first insulating layer and, in a subsequent method step, a conducting layer is applied to the second insulating layer.