Abstract: In one embodiment, an integrated circuit includes a memory array having a plurality of capacitors for storing data of an initial state in the memory array in an initial state. The integrated circuit also includes circuitry for occasionally inverting the data stored by the plurality of capacitors and tracking whether the current state of the data stored by the plurality of capacitors corresponds to the initial state. The circuitry inverts the data read out of the memory array during a read operation when the current state of the data does not correspond to the initial state.

Abstract: The invention relates to a method for arranging chips of a first substrate on a second substrate, in which the chips are grouped at least into first chips and into second chips, the first chips of the first substrate are singulated and the singulated first chips are arranged on the second substrate in such a way that each of the first chips on the second substrate is unambiguously assigned to the associated first chip on the first substrate.

Abstract: A semiconductor wafer includes a dielectric test structure including a voltage line, a control line, and a plurality of test devices connected in parallel to the voltage line and the control line. Each test device includes a voltage-controlled resistor connected to the control line and a dielectric device, the dielectric device being connected to the voltage line via the voltage-controlled resistor. A method for dielectric reliability testing and forming an integrated circuit product is also provided, as is a wafer with a control voltage pad and an integrated circuit product.

Abstract: A system including a tester configured to measure a first current from a first die of neighboring dice and a second current from a second die of the neighboring dice. The tester is configured to compare the first current to the second current to detect damage in the neighboring dice.

Abstract: The invention relates to a method for arranging chips of a first substrate on a second substrate, in which the chips are grouped at least into first chips and into second chips, the first chips of the first substrate are singulated and the singulated first chips are arranged on the second substrate in such a way that each of the first chips on the second substrate is unambiguously assigned to the associated first chip on the first substrate.

Abstract: An implant includes a humidity sensor for generating a signal indicative of humidity within the implant. A controller within the implant receives the signal indicative of humidity, and controls the implant based on the signal indicative of humidity.

Abstract: The invention relates to an electronic switching circuit in which a plurality of test circuit blocks is provided, whereby every test circuit block comprises a first sub-circuit block and at least one second sub-circuit block. A field effect transistor in the first sub-circuit block has a gate insulation layer that is thicker than the gate insulation layer of a field effect transistor in the second sub-circuit block.

Abstract: Some embodiments discussed relate to an apparatus for etching a semiconductor wafer and method for fabricating it, comprising a plurality of electrodes coupled to a power supply for generating a plasma stream and at least one electromagnetic radiation source and a wafer support to position a wafer for etching using the plasma stream and the wafer support having a plurality of apertures to allow passage of electromagnetic radiation from an electromagnetic radiation source through the wafer support to impinge on a surface of the wafer during etching.

Abstract: An integrated circuit device includes a plurality of transistors having gate dielectrics forming logic for the integrated circuit device, a voltage supply line connected to the transistors, and a current measurement device determining when the current in the voltage supply line exceeds a threshold.

Abstract: A semiconductor wafer includes a dielectric test structure including a voltage line, a control line, and a plurality of test devices connected in parallel to the voltage line and the control line. Each test device includes a voltage-controlled resistor connected to the control line and a dielectric device, the dielectric device being connected to the voltage line via the voltage-controlled resistor. A method for dielectric reliability testing and forming an integrated circuit product is also provided, as is a wafer with a control voltage pad and an integrated circuit product.

Abstract: The invention relates to an electronic switching circuit in which a plurality of test circuit blocks is provided, whereby every test circuit block comprises a first sub-circuit block and at least one second sub-circuit block. A field effect transistor in the first sub-circuit block has a gate insulation layer that is thicker than the gate insulation layer of a field effect transistor in the second sub-circuit block.

Abstract: A method eliminates effects of defects on wafers caused by cavities adjacent to the surface of a semiconductor (e.g., silicon) wafer. A first insulating layer is applied to the surface of the semiconductor wafer and into the cavities adjacent to the surface. The applied first insulating layer is covered with a sacrificial layer. A selective back-etching of the sacrificial layer is carried out, such that the cavities adjacent to the surface remain filled with the sacrificial layer. A second insulating layer is applied directly to the first insulating layer and, in a subsequent method step, a conducting layer is applied to the second insulating layer.

Abstract: A surgical instrument (10) is provided that includes a handle (18) defining a longitudinal axis (20). The handle has an outer surface (22) including a plurality of longitudinal fins (24) that define a plurality of longitudinal grooves (26) therebetween. At least one of the longitudinal fins may project radially from the outer surface of the handle. A pair of the fins may project radially from the outer surface of the handle and are diametrically opposed. A pair of the fins may be opposed and disposed in a plane tangential to the outer surface of the handle. Two separate pairs of the fins can project radially from the outer surface of the handle and are diametrically disposed. The two separate pairs are offset 90° relative to the longitudinal axis. Two separate pairs of the fins can be opposed and disposed in alternate planes tangential to the outer surface of the handle.

Abstract: The invention relates to a method for arranging chips of a first substrate on a second substrate, in which the chips are grouped at least into first chips and into second chips, the first chips of the first substrate are singulated and the singulated first chips are arranged on the second substrate in such a way that each of the first chips on the second substrate is unambiguously assigned to the associated first chip on the first substrate.

Abstract: Fluorine is deposited on a semiconductor substrate surface according to a novel process. A semiconductor substrate is placed in a reaction chamber and the substrate surface is wetted with water and/or alcohol. A compound containing fluorine is led to the substrate surface, so that a cleaned semiconductor surface covered with fluorine is produced, and the compound containing fluorine is removed from the reaction chamber. The cleaned semiconductor surface covered with fluorine is then wetted with a mixture containing at least 10% by volume of water and at least 10% by volume of alcohol, for producing a cleaned semiconductor surface covered with a predetermined amount of fluorine. The predetermined amount of fluorine is lower the higher a proportion of water in the mixture is chosen to be. Then, the water and the alcohol are removed from the semiconductor surface.

Abstract: Lateral bipolar transistor, in which a thin diffusion barrier (4) is applied to a base region (10) between an emitter region (9) and a collector region (11), and there is present, on said barrier, a base electrode (8) which is provided for low-resistance supply, is connected to a heavily doped base terminal region and consists of polysilicon, for example, into which dopant is diffused out from said base terminal region.

Abstract: A CMOS circuit has all-around dielectrically insulated source-drain regions. Trenches are formed in the source-drain regions. The trenches are etched onto the mono-crystalline silicon and filled with undoped or very lightly doped silicon. The completely or nearly completely depleted silicon in the trenches represents a dielectrically insulating layer and insulates the source-drain regions towards the adjacent silicon substrate.

Abstract: The present invention provides a method for forming a dielectric 1; 7, 8 on a semiconductor substrate 2 having the following steps: implantation of ions into a surface layer of the semiconductor substrate 2, the ions forming a first dielectric layer 7; and performance of a thermal oxidation process for forming a second dielectric layer 8 on the first dielectric layer 7. Consequently, e.g. by the implantation of nitrogen ions into a surface layer of a silicon substrate, the imperfection density of the dielectric formed can be reduced approximately by a factor of 10.

Abstract: The MOS transistor has field plates and a subarea of the gate formed from the same polysilicon layer. A gate oxide lying underneath them is produced at the beginning of the fabrication process and it therefore exhibits particularly high quality. The polysilicon in the active area is raised to the same level as the adjoining field oxide areas, resulting in a planar topology.

Abstract: The high density integrated semiconductor memory has an EPROM cell in the form of a pillar. The cell has a floating gate and a control gate. The EPROM cell is dimensioned so thin that it is fully depleted. The control gate of the preferred split gate flash EPROM cell or of the dual gate flash EPROM cell is composed of p.sup.+ -doped semiconductor material, so that the fully depleted cylinders exhibit superior lower threshold behavior.