Patents by Inventor Martin Krämer
Martin Krämer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11933314Abstract: A compressor wheel for a compressor of a turbocharger has a hub and a multiplicity of blades on the hub. In intermediate spaces of the multiplicity of blades, a channel is in each case formed between a suction side and a pressure side. The channel guides fluid that flows in axially in relation to a rotation axis radially or radially-axially outward. The hub in relation to the rotation axis is contoured such that the hub has a rotationally symmetrical portion and a non-rotationally symmetrical portion. On the non-rotationally symmetrical portion, a transition between the hub and each of the blades is embodied with a radiused connection and facing the suction side has a region of modified thickness. A region formed by control rays is generated in at least one channel between the suction side and the pressure side on the hub. A method produces the compressor wheel.Type: GrantFiled: August 29, 2022Date of Patent: March 19, 2024Assignee: BorgWarner Inc.Inventors: Martin Schön, Markus Eisenbarth, Manfred Krämer
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Patent number: 11922240Abstract: A multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. The number of bits in the B input is a number of AND-groups and the number of bits in A is the number of AND gates in an AND-group. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges from the charge transfer lines, the charge coupled to an analog to digital converter which forms the dot product output. The charge transfer lines may span multiple unit elements.Type: GrantFiled: December 31, 2020Date of Patent: March 5, 2024Assignee: Ceremorphic, Inc.Inventors: Ryan Boesch, Martin Kraemer, Wei Xiong
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Patent number: 11886835Abstract: A multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. The number of bits in the B input is a number of AND-groups and the number of bits in A is the number of AND gates in an AND-group. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges from the charge transfer lines, the charge coupled to an analog to digital converter which forms the dot product output. The charge transfer lines may span multiple unit elements.Type: GrantFiled: December 31, 2020Date of Patent: January 30, 2024Assignee: Ceremorphic, Inc.Inventors: Ryan Boesch, Martin Kraemer, Wei Xiong
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Patent number: 11743649Abstract: The technology provides for a pair of earbuds. For instance, a first earbud and a second earbud may each include one or more sensors. The pair of earbuds may further include one or more processors configured to receive one or more first sensor signals from a first sensor in the first earbud and one or more second sensor signals from a second sensor in the second earbud. The one or more processors may compare the first sensor signals with the second sensor signals. Based on the comparison, the one or more processors may detect whether the first earbud and the second earbud are being worn by different users. Based on detecting that the first earbud and the second earbud are being worn by different users, the one or more processors may control the first earbud and the second earbud to use a shared mode.Type: GrantFiled: January 8, 2021Date of Patent: August 29, 2023Assignee: Google LLCInventors: Martin Kraemer, Deborah Kathleen Vitus, Dilip Prasanna Kumar, Kristen Lawton, Adam Champy, Christopher Branson, Sandeep Singh Waraich
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Patent number: 11687738Abstract: A Bias Unit Element (UE) has a digital input, a sign input, and a chop clock. The sign input is exclusive ORed with the chop clock to generate a signed chop clock. Each Bias UE comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The chopped sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.Type: GrantFiled: May 31, 2021Date of Patent: June 27, 2023Assignee: Ceremorphic, Inc.Inventors: Martin Kraemer, Ryan Boesch, Wei Xiong
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Patent number: 11689213Abstract: An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspect of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor to form an analog multiplication product as a charge applied to the differential charge transfer bus. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.Type: GrantFiled: May 30, 2021Date of Patent: June 27, 2023Assignee: Ceremorphic, Inc.Inventors: Martin Kraemer, Ryan Boesch, Wei Xiong
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Publication number: 20230146445Abstract: An analog machine learning architecture uses modular analog multiplier-accumulator (AMAC) elements of fixed size to form a machine learning (ML) system with increasing feature map size. A single 3 × 3 × 64 AMAC array is arranged to provide a three layer ML architecture with first layer 3×3×64, second layer 3×3×128, and third layer 3×3×256 using arrangements of single 3×3×64 AMACs arranged in parallel, where the bias of each AMAC is separately established in a unique interval of time.Type: ApplicationFiled: October 31, 2021Publication date: May 11, 2023Applicant: Redpine Signals, Inc.Inventors: Martin KRAEMER, Ryan BOESCH, Wei XIONG
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Patent number: 11593573Abstract: A Unit Element (UE) has a positive UE and a negative UE, each having a digital X input and a digital W input with a sign bit, the sign bit is exclusive ORed with a chop clock to generate a chopped sign bit. The positive UE is enabled when the chopped sign bit is positive and the negative UE is enabled when the chopped sign bit is negative. Each positive and negative UE comprises groups of NAND gates generating an output and complementary output which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The NAND gate outputs and complementary outputs are coupled through binary weighted charge transfer capacitors the positive charge transfer line and negative charge transfer line.Type: GrantFiled: May 31, 2021Date of Patent: February 28, 2023Assignee: Ceremorphic, Inc.Inventors: Martin Kraemer, Ryan Boesch, Wei Xiong
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Patent number: 11567730Abstract: A planar fabrication charge transfer capacitor for coupling charge from a Unit Element (UE) generates a positive charge first output V_PP and a positive charge second output V_NP, the first output coupled to a positive charge line comprising a continuous first planar conductor, a continuous second planar conductor parallel to the first planar conductor, and a continuous third planar conductor parallel to the first planar conductor and second planar conductor, the charge transfer capacitor comprising, in sequence: a first co-planar conductor segment, the first planar conductor, a second co-planar conductor segment, the second planar conductor, a third co-planar conductor segment, the third planar conductor, and a fourth coplanar conductor segment, the first and third coplanar conductor segments capacitively edge coupled to the UE first output V_PP, the second and fourth coplanar conductor segments capacitively edge coupled to the UE second output V_NP.Type: GrantFiled: January 31, 2021Date of Patent: January 31, 2023Assignee: Ceremorphic, Inc.Inventors: Martin Kraemer, Ryan Boesch, Wei Xiong
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Patent number: 11522547Abstract: A Bias Unit Element (UE) has a digital input and sign input, and comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.Type: GrantFiled: May 31, 2021Date of Patent: December 6, 2022Assignee: Ceremorphic, Inc.Inventors: Martin Kraemer, Ryan Boesch, Wei Xiong
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Publication number: 20220383001Abstract: A Unit Element (UE) has a positive UE and a negative UE, each having a digital X input and a digital W input with a sign bit, the sign bit is exclusive ORed with a chop clock to generate a chopped sign bit. The positive UE is enabled when the chopped sign bit is positive and the negative UE is enabled when the chopped sign bit is negative. Each positive and negative UE comprises groups of NAND gates generating an output and complementary output which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The NAND gate outputs and complementary outputs are coupled through binary weighted charge transfer capacitors the positive charge transfer line and negative charge transfer line.Type: ApplicationFiled: May 31, 2021Publication date: December 1, 2022Applicant: Redpine Signals, Inc.Inventors: Martin KRAEMER, Ryan BOESCH, Wei XIONG
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Publication number: 20220385293Abstract: A Bias Unit Element (UE) has a digital input and sign input, and comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.Type: ApplicationFiled: May 31, 2021Publication date: December 1, 2022Applicant: Redpine Signals, Inc.Inventors: Martin KRAEMER, Ryan BOESCH, Wei XIONG
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Publication number: 20220382516Abstract: An architecture for a chopper stabilized multiplier-accumulator (MAC) uses a chop clock and common Unit Element (UE), the MAC formed as a plurality of MAC UEs receiving X and W values and a sign bit exclusive ORed with the chop clock, a plurality of Bias UEs receiving E value and a sign bit exclusive ORed with the chop clock, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.Type: ApplicationFiled: May 31, 2021Publication date: December 1, 2022Applicant: Redpine Signals, Inc.Inventors: Martin KRAEMER, Ryan BOESCH, Wei XIONG
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Publication number: 20220382515Abstract: A Unit Element (UE) has a digital X input and a digital W input, and comprises groups of NAND gates generating complementary outputs which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The number of bits in the X input determines the number of NAND gates in a NAND-group and the number of bits in the W input determines the number of NAND groups. Each NAND-group receives one bit of the W input applied to all of the NAND gates of the NAND-group, and each unit element having the bits of X applied to each associated NAND gate input of each unit element. The NAND gate outputs are coupled through binary weighted charge transfer capacitors to a positive charge transfer line and negative charge transfer line.Type: ApplicationFiled: May 31, 2021Publication date: December 1, 2022Applicant: Redpine Signals, Inc.Inventors: Martin KRAEMER, Ryan BOESCH, Wei XIONG
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Publication number: 20220385301Abstract: An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspect of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor to form an analog multiplication product as a charge applied to the differential charge transfer bus. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.Type: ApplicationFiled: May 30, 2021Publication date: December 1, 2022Applicant: Redpine Signals, Inc.Inventors: Martin KRAEMER, Ryan BOESCH, Wei XIONG
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Publication number: 20220383002Abstract: A Bias Unit Element (UE) has a digital input, a sign input, and a chop clock. The sign input is exclusive ORed with the chop clock to generate a signed chop clock. Each Bias UE comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The chopped sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.Type: ApplicationFiled: May 31, 2021Publication date: December 1, 2022Applicant: Redpine Signals, Inc.Inventors: Martin KRAEMER, Ryan BOESCH, Wei XIONG
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Publication number: 20220382517Abstract: A Gain Balanced Analog Multiply-Accumulator (AMAC) has an inference memory which outputs subsets of inference data comprising X input values and one or more associated W coefficient values. The Gain Balanced AMAC has a number of Analog Multiplier-Accumulator Unit Elements (AMAC UE) in equal number to the number of X input values in each subset of inference data. In each of a series of multiply-accumulate cycles, the X input values and one or more W coefficient values from the inference memory are applied to each AMAC UE to generate a charge corresponding to the multiplication of X input value and W coefficient value of each AMAC UE which is transferred to a shared analog charge bus. The inference memory applies the X input value and W coefficient values of each subset to a different AMAC UE on subsequent cycles to balance the gain of the AMAC such that gain differences from one AMAC UE to another are not cumulative.Type: ApplicationFiled: June 1, 2021Publication date: December 1, 2022Applicant: Redpine Signals, Inc.Inventors: Martin KRAEMER, Ryan BOESCH, Wei XIONG
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Patent number: 11476866Abstract: An Analog to Digital Converter (ADC) for a multiplier accumulator generates a digital output associated with a charge transfer bus made of weighted charge transfer lines with capacitance associated with each charge transfer line, the charge transfer bus connected to groups of ADC unit elements (UE) which add or remove charge from each line of the charge transfer line, each group of ADC unit elements having a sign bit input and a step size input and controlled by an ADC controller which switches the groups of ADC UE in a successive approximation according to a comparison of a summed charge from the weighted charge transfer lines until the ADC UE charge equals the charge transfer line capacitance, each comparison generating a bit value of the digital output.Type: GrantFiled: February 1, 2021Date of Patent: October 18, 2022Assignee: Ceremorphic, Inc.Inventors: Martin Kraemer, Ryan Boesch, Wei Xiong
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Patent number: 11469770Abstract: An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspects of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in AND-groups, each AND gate coupled to a charge transfer bus through a charge transfer capacitor Cu to form an analog multiplication product. Each UE transfers differential charge to the charge transfer bus. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.Type: GrantFiled: January 31, 2021Date of Patent: October 11, 2022Assignee: Ceremorphic, Inc.Inventors: Martin Kraemer, Ryan Boesch, Wei Xiong
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Publication number: 20220283109Abstract: A capacitance sensing system senses frost and ice accumulation in an energy efficient defrost system. The capacitance sensing system comprises a first capacitor including a portion of a metal heat exchanger and a sensor electrode electrically isolated from the metal heat exchanger; a tank oscillator including a second capacitor and an inductor coupled in parallel with each other and with the first capacitor; and a circuit coupled to the tank oscillator. The circuit determines a resonant frequency of the tank oscillator, determines a capacitance value of the first capacitor based on the resonant frequency of the tank oscillator, and transmits a heater activation command in response to determining the capacitance value is greater than a threshold.Type: ApplicationFiled: May 23, 2022Publication date: September 8, 2022Inventors: Bjoern Oliver EVERSMANN, Andreas Felix Martin Kraemer, Michael Seidl