Abstract: An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspects of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in AND-groups, each AND gate coupled to a charge transfer bus through a charge transfer capacitor Cu to form an analog multiplication product. Each UE transfers differential charge to the charge transfer bus. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.

Abstract: A planar fabrication charge transfer capacitor for coupling charge from a Unit Element (UE) generates a positive charge first output V_PP and a positive charge second output V_NP, the first output coupled to a positive charge line comprising a continuous first planar conductor, a continuous second planar conductor parallel to the first planar conductor, and a continuous third planar conductor parallel to the first planar conductor and second planar conductor, the charge transfer capacitor comprising, in sequence: a first co-planar conductor segment, the first planar conductor, a second co-planar conductor segment, the second planar conductor, a third co-planar conductor segment, the third planar conductor, and a fourth coplanar conductor segment, the first and third coplanar conductor segments capacitively edge coupled to the UE first output V_PP, the second and fourth coplanar conductor segments capacitively edge coupled to the UE second output V_NP.

Abstract: A Unit Element (UE) has a digital X input and a digital W input, and comprises groups of NAND gates generating complementary outputs which are coupled to differential charge transfer lines through respective charge transfer capacitor Cu. The number of bits in the X input determines the number of NAND gates in a NAND-group and the number of bits in the W input determines the number of NAND groups. Each NAND-group receives one bit of the W input applied to all of the NAND gates of the NAND-group, and each unit element having the bits of X applied to each associated NAND gate input of each unit element. The NAND gate outputs are coupled through a charge transfer capacitor Cu to charge transfer lines. Multiple Unit Elements may be placed in parallel to sum and scale the charges from the charge transfer lines, the charges coupled to an analog to digital converter which forms the dot product output.

Abstract: A Bias Unit Element (UE) comprises NAND gates with complementary outputs, the complementary outputs coupled through a charge transfer capacitor to a differential charge transfer bus comprising positive charge transfer lines and negative charge transfer lines. Each line of the differential charge transfer bus has a particular binary weighted line weight, such as 1, 2, 4, 2, 4, 8, and 4, 8, 16. Digital bias inputs are provided to the Bias UE NAND gate inputs, with a clear bit to initialize charge, and a sign input for enabling one of a positive Bias UE or negative Bias UE. A low-to-high transition causes a transfer of charge to the binary weighted charge transfer bus, thereby adding or subtracting a bias value from the charge transfer bus.

Abstract: An Analog to Digital Converter (ADC) for a multiplier accumulator generates a digital output associated with a charge transfer bus made of weighted charge transfer lines with capacitance associated with each charge transfer line, the charge transfer bus connected to groups of ADC unit elements (UE) which add or remove charge from each line of the charge transfer line, each group of ADC unit elements having a sign bit input and a step size input and controlled by an ADC controller which switches the groups of ADC UE in a successive approximation according to a comparison of a summed charge from the weighted charge transfer lines until the ADC UE charge equals the charge transfer line capacitance, each comparison generating a bit value of the digital output.

Abstract: A differential multiplier-accumulator accepts A and B digital inputs plus a sign bit and generates a dot product P by applying the bits of the A input and the bits of the B inputs to respective positive and negative unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. One of the positive and negative unit element is enabled by the sign bit, the enabled unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each positive and negative unit element having the bits of A applied to each associated AND gate input of each unit element, which charge to charge transfer lines, and the charge transfer lines are coupled to binary weighted charge summing capacitors and to an analog to digital converter to generate a digital output product.

Abstract: A differential multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to respective positive and negative unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. Each positive and negative unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each positive and negative unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors and to an analog to digital converter to generate a digital output product. The charge transfer lines may span multiple unit elements.

Abstract: A plurality of unit elements share a charge transfer bus, each unit element accepts A and B digital inputs and generates a product P as an analog charge transferred to the charge transfer bus, each unit element comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates of each unit element are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges contributed by all unit elements to the charge transfer lines according to a bit weight and converted to a digital value output.

Abstract: A multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. The number of bits in the B input is a number of AND-groups and the number of bits in A is the number of AND gates in an AND-group. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges from the charge transfer lines, the charge coupled to an analog to digital converter which forms the dot product output. The charge transfer lines may span multiple unit elements.

Abstract: A multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. The number of bits in the B input is a number of AND-groups and the number of bits in A is the number of AND gates in an AND-group. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges from the charge transfer lines, the charge coupled to an analog to digital converter which forms the dot product output. The charge transfer lines may span multiple unit elements.

Abstract: A capacitance sensing system for sensing frost and ice accumulation. The capacitance sensing system comprises a first capacitor formed by a portion of a metal heat exchanger and a sensor electrode electrically isolated from the metal heat exchanger, a tank oscillator comprising a second capacitor and an inductor connected in parallel with each other and coupled in parallel with the first capacitor, and a circuit coupled to the tank oscillator. The circuit coupled to the tank oscillator is configured to determine a resonant frequency of the tank oscillator, determine a capacitance value based on the resonant frequency of the tank oscillator, determine that the capacitance value is greater than a predefined threshold, and transmit a heater activation command in response to determining the capacitance value is greater than the predefined threshold.

Abstract: The technology provides for a pair of earbuds. For instance, a first earbud and a second earbud may each include one or more sensors. The pair of earbuds may further include one or more processors configured to receive one or more first sensor signals from a first sensor in the first earbud and one or more second sensor signals from a second sensor in the second earbud. The one or more processors may compare the first sensor signals with the second sensor signals. Based on the comparison, the one or more processors may detect whether the first earbud and the second earbud are being worn by different users. Based on detecting that the first earbud and the second earbud are being worn by different users, the one or more processors may control the first earbud and the second earbud to use a shared mode.

Abstract: The technology provides for a pair of earbuds. For instance, a first earbud and a second earbud may each include one or more sensors. The pair of earbuds may further include one or more processors configured to receive one or more first sensor signals from a first sensor in the first earbud and one or more second sensor signals from a second sensor in the second earbud. The one or more processors may compare the first sensor signals with the second sensor signals. Based on the comparison, the one or more processors may detect whether the first earbud and the second earbud are being worn by different users. Based on detecting that the first earbud and the second earbud are being worn by different users, the one or more processors may control the first earbud and the second earbud to use a shared mode.

Abstract: The technology provides for a pair of earbuds. For instance, a first earbud and a second earbud may each include one or more sensors. The pair of earbuds may further include one or more processors configured to receive one or more first sensor signals from a first sensor in the first earbud and one or more second sensor signals from a second sensor in the second earbud. The one or more processors may compare the first sensor signals with the second sensor signals. Based on the comparison, the one or more processors may detect whether the first earbud and the second earbud are being worn by different users. Based on detecting that the first earbud and the second earbud are being worn by different users, the one or more processors may control the first earbud and the second earbud to use a shared mode.

Abstract: A capacitance sensing system for sensing frost and ice accumulation. The capacitance sensing system comprises a first capacitor formed by a portion of a metal heat exchanger and a sensor electrode electrically isolated from the metal heat exchanger, a tank oscillator comprising a second capacitor and an inductor connected in parallel with each other and coupled in parallel with the first capacitor, and a circuit coupled to the tank oscillator. The circuit coupled to the tank oscillator is configured to determine a resonant frequency of the tank oscillator, determine a capacitance value based on the resonant frequency of the tank oscillator, determine that the capacitance value is greater than a predefined threshold, and transmit a heater activation command in response to determining the capacitance value is greater than the predefined threshold.

Abstract: A touch-sensitive glass barrier has a conductive coil affixed to the first side of a glass barrier, a capacitor connected to the conductive coil to form a resonator, and an inductance-to-digital converter (LDC) connected to drive an alternating current through the resonator. The LDC determines whether a conductive target has touched the second side of the glass barrier at a point opposite the conductive coil; and responsive to determining that the conductive target has touched the second side of the glass barrier at the point, provides a signal.

Abstract: A touch-sensitive glass barrier has a conductive coil affixed to the first side of a glass barrier, a capacitor connected to the conductive coil to form a resonator, and an inductance-to-digital converter (LDC) connected to drive an alternating current through the resonator. The LDC determines whether a conductive target has touched the second side of the glass barrier at a point opposite the conductive coil; and responsive to determining that the conductive target has touched the second side of the glass barrier at the point, provides a signal.

Abstract: A magnetic field measuring system is disclosed. The magnetic field measuring system includes a substrate, a conductive well formed in the substrate, the well having a first side with a first length, a first contact electrically coupled to the conductive well at a first location of the first side, a second contact electrically coupled to the conductive well at a second location of the first side, wherein the distance between the first location and the second location is less than the first length, a stimulus circuit coupled to the first contact and the second contact, and a sensor for identifying a property indicative of the length of a current path from the first location to the second location through the conductive well.