Abstract: A computer-implemented method includes managing function calls between a plurality of nodes and a super node of a rack system having a distributed operating system (OS). The OS includes a plurality of functions divided into first class and a second class, and each of the plurality of nodes excludes functions in the second class. Managing the function calls includes detecting a call to a first function on a first node of the plurality of nodes. It is determined that the first function belongs to the second class of functions and is not available on the first node. The call to the first function is routed to the super node, responsive to determining that the first function belongs to the second class, where the super node includes code for the functions in the second class.

Abstract: A device is described. The device includes a daughterboard having a first distinct side and a second distinct side. A first connector on the first distinct side is attached to a first baseboard. A second connector on the second distinct side is attached to a second baseboard. A method for attaching a daughterboard to a second device is described. Connectors are included on opposing distinct sides of the daughterboard. The second device includes baseboards mechanically secured in parallel by lead screw actuators. As part of the method, the lead screw actuators are actuated so as to move the baseboards away from each other. A first connector is attached to one of the baseboards. The lead screw actuators are again actuated so as to move the baseboards toward each other until a second connector is brought into attachment with the other of the baseboards.

Abstract: The memory module having a plurality of memory chips and a plurality of connections for connecting the memory module to a processor. At least part of the connections is configurable to be grouped into N sets of address and control connections for N separatively controllable groups of memory chips of the plurality of memory chips (N?2).

Abstract: The sizing of virtual machines is optimized based on projected performance metrics. All virtual machine configuration resources are normalized by a processing device. The normalized resources for the virtual machine configurations are then stored in a catalog. An application is then profiled to obtain resource demand estimates for each virtual machine configuration and a base performance is calculated for the application. The base performance is used to predict performance estimates on all virtual machine configurations in the catalog. Accordingly, a virtual machine configuration having a lowest response time is selected.

Abstract: A communications system that may include a transmitter, a receiver, connected over a communications network. A communication link on the communications network may transfer data between the transmitter and the receiver. The system may also include a logic unit to scramble a plurality of portions of the data at the transmitter based upon the communication link and may unscramble the plurality of portions of the data at the receiver. As a result, the logic unit may provide improved performance of the communication link and/or reduced power consumption of the communication link.

Abstract: Embodiments include methods, computer systems and computer program products for performing superscalar out-of-order processing in software in a computer system. Aspects include: loading opcodes into an analysis thread of the computer system, analyzing opcodes to identify certain non-independent opcode snippets, distributing non-independent opcode snippets to separate threads of computer system, instructing each of separate threads to execute each of non-independent opcode snippets, respectively, and collecting results of executions of each of separate threads by a consolidation thread.

Abstract: A printed circuit board (PCB) assembly includes a first PCB and a second PCB disposed substantially parallel and opposite to each other, such that a second side of the first PCB is opposite to a first side of the second PCB; wherein the second PCB has a first set of side connectors on its first side and a second set of side connectors on its second side, configured for both electrical power supply to and signal communication with the second PCB; the second PCB both electrically and mechanically connected to the second side of the first PCB via a first elastomeric connector; and the second PCB electrically connected to the first PCB via its second set of side connectors and a flexible electrical connector that is electrically connected to the second set of side connectors and the first PCB.

Abstract: A printed circuit board (PCB) assembly includes a first PCB and a second PCB disposed substantially parallel and opposite to each other, such that a second side of the first PCB is opposite to a first side of the second PCB; wherein the second PCB has a first set of side connectors on its first side and a second set of side connectors on its second side, configured for both electrical power supply to and signal communication with the second PCB; the second PCB both electrically and mechanically connected to the second side of the first PCB via a first elastomeric connector; and the second PCB electrically connected to the first PCB via its second set of side connectors and a flexible electrical connector that is electrically connected to the second set of side connectors and the first PCB.

Abstract: A printed circuit board (PCB) assembly includes a first PCB and a second PCB disposed substantially parallel and opposite to each other, such that a second side of the first PCB is opposite to a first side of the second PCB; wherein the second PCB has a first set of side connectors on its first side and a second set of side connectors on its second side, configured for both electrical power supply to and signal communication with the second PCB; the second PCB both electrically and mechanically connected to the second side of the first PCB via a first elastomeric connector; and the second PCB electrically connected to the first PCB via its second set of side connectors and a flexible electrical connector that is electrically connected to the second set of side connectors and the first PCB.

Abstract: A method of memory sharing implemented by logic of a computer memory control unit, the control unit comprising at least one first interface and second interfaces and is adapted to be connected with a main physical memory via the first interface, and a set of N?2 non-cooperative processors via the second interfaces, the logic operatively coupled to the first and second interfaces. The method includes receiving, via the second interfaces, a request to access data of the main physical memory from a first processor of the set; evaluating if a second processor has previously accessed the data requested by the first processor; and deferring the request from the first processor when the evaluation is positive, or, granting the request from the first processor when the evaluation is negative.

Abstract: A persistent caching system is provided. The persistent caching system includes a storage system having a caching server for storing data, and a client for accessing the data through a network. The caching server is configured to store the data in a number of virtual memory blocks. The virtual memory blocks refer to an associated memory-mapped file in a file system of the caching server. The caching server is configured to export addresses of the virtual memory blocks to the client. The client is configured to access at least some of the virtual memory blocks through RDMA using the exported addresses. The caching server is configured to page virtual memory blocks being accessed by one or more clients through RDMA to and/or from the memory-mapped files associated with the accessed virtual memory blocks.

Abstract: The sizing of virtual machines is optimized based on projected performance metrics. All virtual machine configuration resources are normalized by a processing device. The normalized resources for the virtual machine configurations are then stored in a catalogue. An application is then profiled to obtain resource demand estimates for each virtual machine configuration and a base performance is calculated for the application. The base performance is used to predict performance estimates on all virtual machine configurations in the catalogue. Accordingly, a virtual machine configuration having a lowest response time is selected.

Abstract: A method of distributed memory access in a network, the network including a plurality of distributed compute elements, at least one control element and a plurality of distributed memory elements, wherein a data element is striped into data segments, the data segments being imported on at least a number of the distributed memory elements by multiple paths in the network, includes receiving, by a requesting element, credentials including an access permission for accessing the number of distributed memory elements and location information from the control element, the location information indicating physical locations of the data segments on the number of distributed memory elements; and launching, by the requesting element, a plurality of data transfers of the data segments over the multiple paths in the network to and/or from the physical locations.

Abstract: A time-interleaved analog-to-digital converter (ADC) includes a plurality of ADC blocks each including: at least one ADC unit configured to convert an analog input to a digital output; and a digital gain controller configured to adjust a reference voltage of the at least one ADC unit based on a comparison of an actual output of the at least one ADC unit to an expected output of the at least one ADC unit.

Abstract: A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.

Abstract: A time-interleaved analog-to-digital converter (ADC) includes a plurality of ADC blocks each including: at least one ADC unit configured to convert an analog input to a digital output; and a digital gain controller configured to adjust a reference voltage of the at least one ADC unit based on a comparison of an actual output of the at least one ADC unit to an expected output of the at least one ADC unit.

Abstract: A design structure is provided for a reference voltage generator. The design structure includes a first capacitor and an analog to digital converter having its voltage reference coupled to the first capacitor. The first capacitor supplies the voltage reference to the analog to digital converter. A control loop is configured to resupply charges to the first capacitor that are lost when the first capacitor supplies the voltage reference to the analog to digital converter.

Abstract: A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.

Abstract: A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.

Abstract: A design structure is provided for a reference voltage generator. The design structure includes a first capacitor and an analog to digital converter having its voltage reference coupled to the first capacitor. The first capacitor supplies the voltage reference to the analog to digital converter. A control loop is configured to resupply charges to the first capacitor that are lost when the first capacitor supplies the voltage reference to the analog to digital converter.