Abstract: A method is provided for networking nodes in a data center network structure, including connecting at least ten base units each including connected nodes with southbound connections of a multi-host NIC controller having northbound a higher total bandwidth than southbound, the controllers configured as dragonfly switches; connecting the ten base units with their respective controllers in a modified Peterson graph form as an intragroup network to build a super unit including three groups, where each controller uses three northbound connections for a direct connection to three other base units of the super unit, and in which two base units of each group are connected via a respective one of a fourth northbound connection to one of the other groups, and a remaining base unit not being part of one of the groups is adapted for using three northbound connections for direct connection to one base unit in each group.

Abstract: A method is provided for networking nodes in a data center network structure, including connecting at least ten base units each including connected nodes with southbound connections of a multi-host NIC controller having northbound a higher total bandwidth than southbound, the controllers configured as dragonfly switches; connecting the ten base units with their respective controllers in a modified Peterson graph form as an intragroup network to build a super unit including three groups, where each controller uses three northbound connections for a direct connection to three other base units of the super unit, and in which two base units of each group are connected via a respective one of a fourth northbound connection to one of the other groups, and a remaining base unit not being part of one of the groups is adapted for using three northbound connections for direct connection to one base unit in each group.

Abstract: A method is provided for networking nodes in a data center network structure, including connecting at least ten base units each including connected nodes with southbound connections of a multi-host NIC controller having northbound a higher total bandwidth than southbound, the controllers configured as dragonfly switches; connecting the ten base units with their respective controllers in a modified Peterson graph form as an intragroup network to build a super unit including three groups, where each controller uses three northbound connections for a direct connection to three other base units of the super unit, and in which two base units of each group are connected via a respective one of a fourth northbound connection to one of the other groups, and a remaining base unit not being part of one of the groups is adapted for using three northbound connections for direct connection to one base unit in each group.

Abstract: Embodiments of the present invention are directed to an integrated circuit (IC) package assembly. The IC package assembly includes a base printed circuit board (PCB), and a set of IC packages. Each of the IC packages includes at least one IC chip, mounted on or partly in a support component, which mechanically supports and electrically connects to the IC chip. In addition, each of the IC packages is laterally soldered to the base PCB (e.g., a motherboard PCB) and arranged transversally to the base PCB and forms an angle ? therewith. As a result, a slanted stack of IC packages is obtained, wherein the IC packages are essentially parallel to each other. Further embodiments are directed to related devices, including the above assembly, and to related fabrication methods.

Abstract: A method is provided for networking nodes in a data center network structure, including connecting at least ten base units each including connected nodes with southbound connections of a multi-host NIC controller having northbound a higher total bandwidth than southbound, the controllers configured as dragonfly switches; connecting the ten base units with their respective controllers in a modified Peterson graph form as an intragroup network to build a super unit including three groups, where each controller uses three northbound connections for a direct connection to three other base units of the super unit, and in which two base units of each group are connected via a respective one of a fourth northbound connection to one of the other groups, and a remaining base unit not being part of one of the groups is adapted for using three northbound connections for direct connection to one base unit in each group.

Abstract: Embodiments of the invention are directed to an integrated circuit (IC) package assembly, including: one or more printed circuit boards (PCBs); and a set of chip packages, each including: an overmold; and an IC chip, overmolded in the overmold, and wherein: the chip packages are stacked transversely to an average plane of each of the chip packages, thereby forming a stack wherein a main surface of one of the chip packages faces a main surface of another one of the chip packages; and each of the chip packages is laterally soldered to one or more of said one or more PCBs and arranged transversally to each of said one or more PCBs, whereby an average plane of each of said one or more PCBs extends transversely to the average plane of each of the chip packages of the stack. Further embodiments are directed to related devices and fabrication methods.

Abstract: Embodiments of the present invention are directed to an integrated circuit (IC) package assembly. The IC package assembly includes a base printed circuit board (PCB), and a set of IC packages. Each of the IC packages includes at least one IC chip, mounted on or partly in a support component, which mechanically supports and electrically connects to the IC chip. In addition, each of the IC packages is laterally soldered to the base PCB (e.g., a motherboard PCB) and arranged transversally to the base PCB and forms an angle ? therewith. As a result, a slanted stack of IC packages is obtained, wherein the IC packages are essentially parallel to each other. Further embodiments are directed to related devices, including the above assembly, and to related fabrication methods.

Abstract: Embodiments of the invention are directed to an integrated circuit (IC) package assembly, including: one or more printed circuit boards (PCBs); and a set of chip packages, each including: an overmold; and an IC chip, overmolded in the overmold, and wherein: the chip packages are stacked transversely to an average plane of each of the chip packages, thereby forming a stack wherein a main surface of one of the chip packages faces a main surface of another one of the chip packages; and each of the chip packages is laterally soldered to one or more of said one or more PCBs and arranged transversally to each of said one or more PCBs, whereby an average plane of each of said one or more PCBs extends transversely to the average plane of each of the chip packages of the stack. Further embodiments are directed to related devices and fabrication methods.

Abstract: An inductor including a primary coil coaxially arranged and operated in parallel with isolated secondary coils each including at least one loop winding with two open-circuited ports. At least one phase shifting device is arranged between open-circuited ports of at least one secondary coil. A method to operate an inductor by combining primary and secondary coils with phase shifting devices to get a wide tuning range is also provided. The method includes the step of phase shifting open-circuited ports of at least one secondary coil.

Abstract: An interfacing apparatus and related method is provided for configuring to couple a plurality of memory devices being addressable by means of an address space to a processing unit. In one embodiment, the apparatus comprises a first memory access unit being adapted for receiving a memory address from said processing unit and for accessing said memory devices accordingly based on the address provided. It also comprises a second memory access unit being adapted for receiving content data from the processing unit and for controlling a search or update function accordingly for the received content data in one or more of the memory devices. In addition, an allocation unit is also provided for allocating a first part of the address space of the memory devices to said first memory access unit and allocating a second part of the address space of said memory devices to the second memory access unit, each of the memory access units being assigned to corresponding memory devices of the plurality of memory devices.

Abstract: An analog-digital converter includes converter units and a control unit. The converter units each including a comparator for performing a comparison using an input voltage, one or more capacitor ladders each having a signal line connected with first terminals of capacitors and with one input of the comparator, and switches each of which is associated with one of the capacitors, connected to a second terminal of the respective capacitor with a first or a second reference potential, the input voltage being shifted when switching one or more of the switches. The control unit controls the number of converter units, and to set the switching states of the plurality of switches in conversion cycles and to obtain comparison results from each of the comparators in a comparison subsequent to each setting of the switching states.

Abstract: An inductor including a primary coil coaxially arranged and operated in parallel with isolated secondary coils each including at least one loop winding with two open-circuited ports. At least one phase shifting device is arranged between open-circuited ports of at least one secondary coil. A method to operate an inductor by combining primary and secondary coils with phase shifting devices to get a wide tuning range is also provided. The method includes the step of phase shifting open-circuited ports of at least one secondary coil.

Abstract: An inductor including a primary coil coaxially arranged and operated in parallel with isolated secondary coils each including at least one loop winding with two open-circuited ports. At least one phase shifting device is arranged between open-circuited ports of at least one secondary coil. A method to operate an inductor by combining primary and secondary coils with phase shifting devices to get a wide tuning range is also provided. The method includes the step of phase shifting open-circuited ports of at least one secondary coil.

Abstract: An analog-digital converter includes converter units and a control unit. The converter units each including a comparator for performing a comparison using an input voltage, one or more capacitor ladders each having a signal line connected with first terminals of capacitors and with one input of the comparator, and switches each of which is associated with one of the capacitors, connected to a second terminal of the respective capacitor with a first or a second reference potential, the input voltage being shifted when switching one or more of the switches. The control unit controls the number of converter units, and to set the switching states of the plurality of switches in conversion cycles and to obtain comparison results from each of the comparators in a comparison subsequent to each setting of the switching states.

Abstract: The communication system having a transmitter and a receiver, wherein the transmitter and the receiver are coupled by a clock channel and a data channel, wherein the clock channel is shorter than the data channel and wherein the receiver comprises a delay circuit for extracting a jitter signal from a clock channel signal, delaying the extracted jitter signal, and generating a receiver clock signal for the receiver by the delayed jitter signal.

Abstract: A receiver for a serial link port that is enhanced by a clock-data-recovery loop connected to the forwarded clock signal lane. The receiver includes a phase interpolation means controlled by a phase position logic which gets its update signal from local phase update signals of the clock-data-recovery loop via a digital low pass filter. The receiver also provides a global phase update source selection logic to control which clock-data-recovery loop is distributing phase update information, and which clock-data-recovery loop is receiving phase update information based on the clock analysis block.

Abstract: Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data signal are disclosed. In particular, embodiments extend the CDR loop by slowing the clock rate with respect to the sampling clock. For instance, the slower clock rate may be implemented by dividing the frequency of the sampling clock by a number such as 128, slowing a sampling clock frequency designed to handle multiple gigabits per second (Gbps) to a frequency of less than one kilohertz (Khz). In addition to the reduced power consumption realized by operating at a lower frequency, the slower clock rate allows components of the CDR loop circuitry to operate a lower operating voltage reducing power consumption by the CDR loop even more.

Abstract: A system and method for cross talk compensation in serial link busses, the method including: evaluating if a positive potential or a negative potential is being received by a receiver of a victim from an aggressor is dominant; measuring the distance between an incident signal and a decision threshold to obtain a positive or negative value; and using the positive or negative sign as a recovered bit value if positive potential or a negative potential is being received by a receiver of a victim from an aggressor is not dominant and using the sign of the positive potential or a negative potential that is being received by a receiver of a victim from an aggressor if this is dominant.

Abstract: A continuously tunable inductor with an inductive-capacitive (LC) voltage controlled oscillator (VCO) having a primary coil. The inductor includes a separate isolated secondary coil, a set of transistors composing a closed loop with the secondary coil, a magnetic coupling between the primary coil of the LC VCO and the secondary coil, an electrical coupling between the LC VCO and the set of transistors composing a closed loop with the secondary coil, and means for electric current injection into the closed loop. Such an inductor can be tuned by modulating a mutual inductance, which is magnetically and electrically coupled with the LC VCO by injection of an electric current (I0).

Abstract: An inductor and method of operating the inductor by combining primary and secondary coils with passive coupling, active parallel, or active cross-coupling structures. The first includes at least one passive coupling structure having at least one coupling coil arranged between a primary coil and at least one of the secondary coils and/or between two of the secondary coils. The second includes an active coupling structure arranged between a primary coil and at least one secondary coil and/or between at least two of the secondary coils, to selectively parallel couple the primary coil and one of the secondary coils and/or at least two of the secondary coils. The third includes an active coupling structure to selectively cross couple a primary coil and at least one of the secondary coils and/or to selectively cross couple at least two of the secondary coils.