Abstract: A detector for detecting electromagnetic waves, the detector having an antenna for receiving the electromagnetic waves, a semiconductor element, wherein a termination section of the semiconductor element establishes a termination resistor of the antenna, wherein the termination section is provided for heating a temperature-sensitive part of the semiconductor element, wherein the semiconductor element comprises a temperature-dependent characteristic that is dependent from the temperature of the temperature sensitive part and a measurement unit for measuring the temperature-dependent characteristic of the semiconductor element.

Abstract: A system and method for cross talk compensation in serial link busses, the method comprising: evaluating if a positive potential or a negative potential is being received by a receiver of a victim from an aggressor is dominant; measuring the distance between an incident signal and a decision threshold to obtain a positive or negative value; and using the positive or negative sign as a recovered bit value if positive potential or a negative potential is being received by a receiver of a victim from an aggressor is not dominant and using the sign of the positive potential or a negative potential that is being received by a receiver of a victim from an aggressor if this is dominant.

Abstract: A signal generator device for generating at least one periodic signal for use in a data eye scan system. The signal generator comprises a clock input, at least one output and at least one signal generator coupled with the clock input and with the output. The signal generator is at least one token ring with a predetermined number of positions and is operable to propagate at least one token in the ring by moving the token from its current position to a following position dependent on a clock signal from the clock input. The signal generator further comprises a predetermined number of signal value units that each represent a respective predetermined signal value of a predetermined signal waveform and are operable to provide the signal value at an output of the signal generator dependent on a current position of the at least one token in the token ring.

Abstract: A driver circuit is provided comprising at least two equal main units (MU) each comprising at least two sub units (SU) coupled to a data output (dout). Each sub unit (SU) is adapted to represent a respective predetermined impedance. Each main unit (MU) is adapted to that, when in a data mode, each sub unit (SU) of the respective main unit (MU) is switchable to either a first or second reference potential depending on a data signal to transmit. Each main unit (MU) is further adapted to that, when in a termination mode, the sub units (SU) of the respective main unit (MU) are switched to either the first or second reference potential such that an output of the respective main unit (MU) is neutral with respect to the driving of the data output (dout) to the first or second reference potential.

Abstract: A receiver for a serial link port that is enhanced by a clock-data-recovery loop connected to the forwarded clock signal lane. The receiver includes a phase interpolation means controlled by a phase position logic which gets its update signal from local phase update signals of the clock-data-recovery loop via a digital low pass filter. The receiver also provides a global phase update source selection logic to control which clock-data-recovery loop is distributing phase update information, and which clock-data-recovery loop is receiving phase update information based on the clock analysis block.

Abstract: A signal generator for generating multiple phases includes a ring oscillator with at least one first adjustable delay stage and at least one second delay stage being serially arranged, wherein an output of the first delay stage is provided for delivering at least one first output phase and an output of the second delay stage is provided for delivering at least one second output phase, and an adjustment circuit for adjusting the delay of the first adjustable delay stage, wherein the adjustment circuit is provided for adjusting the phase relationship between the first output phase and the second output phase by means of setting a first propagation delay for the first delay stage.

Abstract: A receiver for a serial link port that is enhanced by a clock-data-recovery loop connected to the forwarded clock signal lane. The receiver includes a phase interpolation means controlled by a phase position logic which gets its update signal from local phase update signals of the clock-data-recovery loop via a digital low pass filter. The receiver also provides a global phase update source selection logic to control which clock-data-recovery loop is distributing phase update information, and which clock-data-recovery loop is receiving phase update information based on the clock analysis block.

Abstract: A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL), a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.

Abstract: A system for synchronizing interconnects in a link system according to various embodiments can include a computer configured to receive input data at a transmit side, the transmit side including at least one pseudo-random bit sequence scrambler; scramble the input data at the transmit side via the pseudo-random bit scrambler with dual tap sequences resulting in scrambled data; transmit the scrambled data with the dual tap sequences along all lanes of a plurality of lanes to a receive side via a bus interconnecting the plurality of lanes, the receive side including at least one pseudo-random bit sequence descrambler, and the receive side directly connected to the transmit side via the bus; synchronize the at least one pseudo-random bit sequence scrambler to the at least one pseudo-random bit sequence descrambler; and de-scramble the transmitted scrambled data at the receive side resulting in the input data.

Abstract: An inductor and method of operating the inductor by combining primary and secondary coils with passive coupling, active parallel, or active cross-coupling structures. The first includes at least one passive coupling structure having at least one coupling coil arranged between a primary coil and at least one of the secondary coils and/or between two of the secondary coils. The second includes an active coupling structure arranged between a primary coil and at least one secondary coil and/or between at least two of the secondary coils, to selectively parallel couple the primary coil and one of the secondary coils and/or at least two of the secondary coils. The third includes an active coupling structure to selectively cross couple a primary coil and at least one of the secondary coils and/or to selectively cross couple at least two of the secondary coils.

Abstract: A continuously tunable inductor with an inductive-capacitive (LC) voltage controlled oscillator (VCO) having a primary coil. The inductor includes a separate isolated secondary coil, a set of transistors composing a closed loop with the secondary coil, a magnetic coupling between the primary coil of the LC VCO and the secondary coil, an electrical coupling between the LC VCO and the set of transistors composing a closed loop with the secondary coil, and means for electric current injection into the closed loop. Such an inductor can be tuned by modulating a mutual inductance, which is magnetically and electrically coupled with the LC VCO by injection of an electric current (I0).

Abstract: An inductor including a primary coil coaxially arranged and operated in parallel with isolated secondary coils each including at least one loop winding with two open-circuited ports. At least one phase shifting device is arranged between open-circuited ports of at least one secondary coil. A method to operate an inductor by combining primary and secondary coils with phase shifting devices to get a wide tuning range is also provided. The method includes the step of phase shifting open-circuited ports of at least one secondary coil.

Abstract: A method and system for decision feedback equalization for digital transmission systems is provided. Low-power integrating decision feedback equalization with fast switched-capacitor paths are used, for suppressing intersymbol interference (ISI) due to past data symbols. The decision feedback equalization involves performing current-integrating decision feedback equalization at low-power employing a fast capacitively coupled feed-forward path at the output of a current-integrating buffer and inducing voltage changes by charge redistribution via coupled switching capacitors, and performing a voltage digital-to-analog conversation to determine a feedback coefficient as a coupling voltage. Then switches are reset to a pre-charge coupling voltage in the buffers to eliminate residual ISI caused by signal history, thereby achieving current integrating buffering with switched-capacitor feedback during the integration, and the capacitive switches are triggered by previous symbols.

Abstract: A method for synchronizing interconnects in a link system according to various embodiments can include receiving input data at a transmit side, the transmit side including at least one pseudo-random bit sequence scrambler; scrambling the input data at the transmit side via the pseudo-random bit scrambler with dual tap sequences resulting in scrambled data; transmitting the scrambled data with the dual tap sequences along all lanes of a plurality of lanes to a receive side via a bus interconnecting the plurality of lanes, the receive side including at least one pseudo-random bit sequence descrambler; synchronizing the at least one pseudo-random bit sequence scrambler to the at least one pseudo-random bit sequence descrambler; using an edge detection or transition detection device for synchronization of the descrambler to the scrambler; and de-scrambling the transmitted scrambled data at the receive side resulting in the input data.

Abstract: A signal generator for generating multiple phases includes a ring oscillator with at least one first adjustable delay stage and at least one second delay stage being serially arranged, wherein an output of the first delay stage is provided for delivering at least one first output phase and an output of the second delay stage is provided for delivering at least one second output phase, and an adjustment circuit for adjusting the delay of the first adjustable delay stage, wherein the adjustment circuit is provided for adjusting the phase relationship between the first output phase and the second output phase by means of setting a first propagation delay for the first delay stage.

Abstract: An apparatus and a corresponding method for coupling a memory device being addressable by means of an address space to a processing unit, the apparatus consisting: a first memory access unit being adapted for receiving a memory address from the processing unit and for accessing the memory device by the received memory address; a second memory access unit being adapted for receiving content data (an input key) from the processing unit and for controlling a search for the received content data in the memory device, and an allocation unit for allocating a first part of the address space of the memory device to the first memory access unit and a second part of the address space of the memory device to the second memory access unit. A storage medium to perform coupling a memory device being addressable by means of an address space to a processing unit is also provided.

Abstract: A driver circuit is provided comprising at least two equal main units (MU) each comprising at least two sub units (SU) coupled to a data output (dout). Each sub unit (SU) is adapted to represent a respective predetermined impedance. Each main unit (MU) is adapted to that, when in a data mode, each sub unit (SU) of the respective main unit (MU) is switchable to either a first or second reference potential depending on a data signal to transmit. Each main unit (MU) is further adapted to that, when in a termination mode, the sub units (SU) of the respective main unit (MU) are switched to either the first or second reference potential such that an output of the respective main unit (MU) is neutral with respect to the driving of the data output (dout) to the first or second reference potential.

Abstract: Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data signal are disclosed. In particular, embodiments extend the CDR loop by slowing the clock rate with respect to the sampling clock. For instance, the slower clock rate may be implemented by dividing the frequency of the sampling clock by a number such as 128, slowing a sampling clock frequency designed to handle multiple gigabits per second (Gbps) to a frequency of less than one kilohertz (Khz). In addition to the reduced power consumption realized by operating at a lower frequency, the slower clock rate allows components of the CDR loop circuitry to operate a lower operating voltage reducing power consumption by the CDR loop even more.

Abstract: A detector for detecting electromagnetic waves, the detector having an antenna for receiving the electromagnetic waves, a semiconductor element, wherein a termination section of the semiconductor element establishes a termination resistor of the antenna, wherein the termination section is provided for heating a temperature-sensitive part of the semiconductor element, wherein the semiconductor element comprises a temperature-dependent characteristic that is dependent from the temperature of the temperature sensitive part and a measurement unit for measuring the temperature-dependent characteristic of the semiconductor element.

Abstract: A signal generator device for generating at least one periodic signal for use in a data eye scan system. The signal generator comprises a clock input, at least one output and at least one signal generator coupled with the clock input and with the output. The signal generator is at least one token ring with a predetermined number of positions and is operable to propagate at least one token in the ring by moving the token from its current position to a following position dependent on a clock signal from the clock input. The signal generator further comprises a predetermined number of signal value units that each represent a respective predetermined signal value of a predetermined signal waveform and are operable to provide the signal value at an output of the signal generator dependent on a current position of the at least one token in the token ring.