Patents by Inventor Martin M. Frank
Martin M. Frank has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120306019Abstract: A semiconductor device includes a first field effect transistor (FET) and a second FET located on a substrate, the first FET comprising a first interfacial oxide layer, and the second FET comprising a second interfacial oxide layer, wherein the second interfacial oxide layer of the second FET is thicker than the first interfacial oxide layer of the first FET; and a recess located in the substrate adjacent to the second FET.Type: ApplicationFiled: August 10, 2012Publication date: December 6, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jin Cai, Eduard A. Cartier, Martin M. Frank, Marwan H. Khater
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Publication number: 20120292677Abstract: Ferroelectric semiconductor switching devices are provided, including field effect transistor (FET) devices having gate stack structures formed with a ferroelectric layer disposed between a gate contact and a thin conductive layer (“quantum conductive layer”) . The gate contact and ferroelectric layer serve to modulate an effective work function of the thin conductive layer. The thin conductive layer with the modulated work function is coupled to a semiconductor channel layer to modulate current flow through the semiconductor and achieve a steep sub-threshold slope.Type: ApplicationFiled: May 16, 2011Publication date: November 22, 2012Applicant: International Business Machines CorporationInventors: Catherine A. Dubourdieu, David J. Frank, Martin M. Frank, Vijay Narayanan, Paul M. Solomon, Thomas N. Theis
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Publication number: 20120286340Abstract: A method of controlling ferroelectric characteristics of integrated circuit device components includes forming a ferroelectrically controllable dielectric layer over a substrate; and forming a stress exerting structure proximate the ferroelectrically controllable dielectric layer such that a substantially uniaxial strain is induced in the ferroelectrically controllable dielectric layer by the stress exerting structure; wherein the ferroelectrically controllable dielectric layer comprises one or more of: a ferroelectric oxide layer and a normally non-ferroelectric material layer that does not exhibit ferroelectric properties in the absence of an applied stress.Type: ApplicationFiled: July 25, 2012Publication date: November 15, 2012Applicants: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Martin M. Frank, Catherine A. Dubourdieu
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Patent number: 8304306Abstract: A method for forming a semiconductor device includes forming a first field effect transistor (FET) and a second FET on a substrate, the first FET comprising a first interfacial oxide layer, and the second FET comprising a second interfacial oxide layer; encapsulating the first interfacial oxide layer of the first FET; and performing lateral oxidation of the second interfacial oxide layer of the second FET, wherein the lateral oxidation of the second interfacial oxide layer of the second FET converts a portion of the substrate located underneath the second FET into additional interfacial oxide.Type: GrantFiled: March 28, 2011Date of Patent: November 6, 2012Assignee: International Business Machines CorporationInventors: Jin Cai, Eduard A. Cartier, Martin M. Frank, Marwan H. Khater
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Publication number: 20120248537Abstract: A method for forming a semiconductor device includes forming a first field effect transistor (FET) and a second FET on a substrate, the first FET comprising a first interfacial oxide layer, and the second FET comprising a second interfacial oxide layer; encapsulating the first interfacial oxide layer of the first FET; and performing lateral oxidation of the second interfacial oxide layer of the second FET, wherein the lateral oxidation of the second interfacial oxide layer of the second FET converts a portion of the substrate located underneath the second FET into additional interfacial oxide.Type: ApplicationFiled: March 28, 2011Publication date: October 4, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jin Cai, Eduard A. Cartier, Martin M. Frank, Marwan H. Khater
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Publication number: 20120228773Abstract: A layered structure and semiconductor device and methods for fabricating a layered structure and semiconductor device. The layered structure includes: a base layer including a material containing titanium nitride, tantalum nitride, or a combination thereof; a conductive layer including a material containing: tantalum aluminum nitride, titanium aluminum nitride, tantalum silicon nitride, titanium silicon nitride, tantalum hafnium nitride, titanium hafnium nitride, hafnium nitride, hafnium carbide, tantalum carbide, vanadium nitride, niobium nitride, or any combination thereof; and a tungsten layer. The semiconductor device includes: a semiconductor substrate; a base layer; a conductive layer; and a tungsten layer.Type: ApplicationFiled: March 8, 2011Publication date: September 13, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen L. Brown, John Bruley, Cyril Cabral, JR., Sandro Callegari, Martin M. Frank, Michael A. Guillorn, Marinus Hopstaken, Vijay Narayanan, Keith Kwong Hon Wong
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Publication number: 20120193716Abstract: A semiconductor structure includes a high-k dielectric layer over a semiconductor substrate; and a gate layer over the high-k dielectric layer, wherein the gate layer has a negative electrical bias during anneal.Type: ApplicationFiled: April 9, 2012Publication date: August 2, 2012Applicant: International Business Machines CorporationInventor: Martin M. Frank
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Publication number: 20120193348Abstract: An apparatus includes a wafer annealing tool and a plurality of electrodes coupled to the wafer annealing tool, wherein the electrodes are configured to be in physical contact with a wafer so that, when the wafer is annealed, a negative electrical bias is formed across one or more gate stacks of the wafer.Type: ApplicationFiled: April 9, 2012Publication date: August 2, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Martin M. Frank
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Publication number: 20120181610Abstract: Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.Type: ApplicationFiled: March 29, 2012Publication date: July 19, 2012Applicant: International Business Machines CorporationInventors: Martin M. Frank, Arvind Kumar, Vijay Narayanan, Vamsi K. Paruchuri, Jeffrey Sleight
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Patent number: 8212322Abstract: Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.Type: GrantFiled: March 9, 2010Date of Patent: July 3, 2012Assignee: International Business Machines CorporationInventors: Martin M. Frank, Arvind Kumar, Vijay Narayanan, Vamsi K. Paruchuri, Jeffrey Sleight
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Publication number: 20120147666Abstract: An example embodiment disclosed is a phase change memory cell. The memory cell includes a phase change material and a transducer positioned proximate the phase change material. The phase change material is switchable between at least an amorphous state and a crystalline state. The transducer is configured to activate when the phase change material is changed from the amorphous state to the crystalline state. In a particular embodiment, the transducer is ferroelectric material.Type: ApplicationFiled: December 10, 2010Publication date: June 14, 2012Applicants: Centre National de la Recherche Scientifique, International Business Machines CorporationInventors: Catherine A. Dubourdieu, Martin M. Frank, Bipin Rajendran, Alejandro G. Schrott
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Patent number: 8193051Abstract: The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride.Type: GrantFiled: March 14, 2011Date of Patent: June 5, 2012Assignee: International Business Machines CorporationInventors: Nestor A. Bojarczuk, Jr., Cyril Cabral, Jr., Eduard A. Cartier, Matthew W. Copel, Martin M. Frank, Evgeni P. Gousev, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri
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Patent number: 8178382Abstract: A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium layer are patterned and encapsulated by a dielectric cap portion, a dielectric spacer, and the first silicon germanium layer. The silicon germanium layer is removed between the first and second silicon layers to form a silicon germanium mesa structure that structurally support an overhanging structure comprising a stack of a silicon portion, a silicon germanium alloy portion, a germanium photodetector, and a dielectric cap portion. The germanium photodetector is suspended by the silicon germanium mesa structure and does not abut a silicon waveguide. Germanium diffusion into the silicon waveguide and defect density in the germanium detector are minimized.Type: GrantFiled: January 13, 2011Date of Patent: May 15, 2012Assignee: International Business Machines CorporationInventors: Solomon Assefa, Jack O. Chu, Martin M. Frank, William M. Green, Young-hee Kim, George G. Totir, Joris Van Campenhout, Yurri A. Vlasov, Ying Zhang
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Publication number: 20110241091Abstract: A method of controlling ferroelectric characteristics of integrated circuit device components includes forming a ferroelectrically controllable dielectric layer over a substrate; and forming a stress exerting structure proximate the ferroelectrically controllable dielectric layer such that a substantially uniaxial strain is induced in the ferroelectrically controllable dielectric layer by the stress exerting structure; wherein the ferroelectrically controllable dielectric layer comprises one or more of: a ferroelectric oxide layer and a normally non-ferroelectric material layer that does not exhibit ferroelectric properties in the absence of an applied stress.Type: ApplicationFiled: April 2, 2010Publication date: October 6, 2011Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUEInventors: Catherine A. Dubourdieu, Martin M. Frank
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Publication number: 20110207280Abstract: A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MxOy?2x/y M+SiO2 is positive 2) a metal that has a more negative Gibbs free energy per oxygen atom for formation of oxide than the material of the lower metal layer and the material of the upper metal layer. The scavenging metal layer meeting these criteria captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric. In addition, the scavenging metal layer remotely reduces the thickness of a silicon oxide interfacial layer underneath the high-k dielectric. As a result, the equivalent oxide thickness (EOT) of the total gate dielectric is reduced and the field effect transistor maintains a constant threshold voltage even after high temperature processes during CMOS integration.Type: ApplicationFiled: May 3, 2011Publication date: August 25, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takashi Ando, Changhwan Choi, Martin M. Frank, Vijay Narayanan
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Patent number: 7989902Abstract: A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MxOy?2x/y M+SiO2 is positive 2) a metal that has a more negative Gibbs free energy per oxygen atom for formation of oxide than the material of the lower metal layer and the material of the upper metal layer. The scavenging metal layer meeting these criteria captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric. In addition, the scavenging metal layer remotely reduces the thickness of a silicon oxide interfacial layer underneath the high-k dielectric. As a result, the equivalent oxide thickness (EOT) of the total gate dielectric is reduced and the field effect transistor maintains a constant threshold voltage even after high temperature processes during CMOS integration.Type: GrantFiled: June 18, 2009Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventors: Takashi Ando, Changhwan Choi, Martin M. Frank, Vijay Narayanan
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Publication number: 20110175176Abstract: A method for forming a semiconductor structure is disclosed. The method includes forming a high-k dielectric layer over a semiconductor substrate and forming a gate layer over the high-k dielectric layer. The method also includes heating the gate layer to 350° C., wherein, if the gate layer includes non-conductive material, the non-conductive material becomes conductive. The method further includes annealing the substrate, the high-k dielectric layer, and the gate layer in excess of 350° C. and, during the annealing, applying a negative electrical bias to the gate layer relative to the semiconductor substrate. A semiconductor structure is also disclosed. The semiconductor structure includes a high-k dielectric layer over a semiconductor substrate, and a gate layer over the high-k dielectric layer. The gate layer has a negative electrical bias during anneal. A p-channel FET including this semiconductor structure is also disclosed.Type: ApplicationFiled: January 20, 2010Publication date: July 21, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Martin M. Frank
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Publication number: 20110175147Abstract: A field effect transistor device and method which includes a semiconductor substrate, a dielectric gate layer, preferably a high dielectric constant gate layer, overlaying the semiconductor substrate and an electrically conductive oxygen barrier layer overlaying the gate dielectric layer. In one embodiment, there is a conductive layer between the gate dielectric layer and the oxygen barrier layer. In another embodiment, there is a low resistivity metal layer on the oxygen barrier layer.Type: ApplicationFiled: January 20, 2010Publication date: July 21, 2011Applicant: International Business Machines CorporationInventors: Praneet Adusumilli, Alessandro Callegari, Josephine B. Chang, Changhwan Choi, Martin M. Frank, Michael A. Guillorn, Vijay Narayanan
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Publication number: 20110165767Abstract: The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride.Type: ApplicationFiled: March 14, 2011Publication date: July 7, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nestor A. Bojarczuk, JR., Cyril Cabral, JR., Eduard A. Cartier, Matthew W. Copel, Martin M. Frank, Evgeni P. Gousev, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri
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Publication number: 20110143482Abstract: A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium layer are patterned and encapsulated by a dielectric cap portion, a dielectric spacer, and the first silicon germanium layer. The silicon germanium layer is removed between the first and second silicon layers to form a silicon germanium mesa structure that structurally support an overhanging structure comprising a stack of a silicon portion, a silicon germanium alloy portion, a germanium photodetector, and a dielectric cap portion. The germanium photodetector is suspended by the silicon germanium mesa structure and does not abut a silicon waveguide. Germanium diffusion into the silicon waveguide and defect density in the germanium detector are minimized.Type: ApplicationFiled: January 13, 2011Publication date: June 16, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Solomon Assefa, Jack O. Chu, Martin M. Frank, William M. Green, Young-hee Kim, George G. Totir, Joris Van Campenhout, Yurri A. Vlasov, Ying Zhang