Abstract: A semiconductor device and method of manufacturing thereof. The semiconductor device has at least one NMOS device and at least one PMOS device provided on a substrate. An electron channel of the NMOS device is aligned with a first direction. A hole channel of the PMOS device is aligned with a different second direction that forms an acute angle with respect to the first direction.

Abstract: A memory cell having three transistors and a capacitor having metallic electrodes is described. Multiple memory cells may be arranged in a memory unit or array. Collective electrodes may be used in a space-saving embodiment of the capacitor.

Abstract: A method of operating a memory cell, a memory cell and a memory unit are described. For example, a memory cell comprises a capacitance and an access circuit in association with said capacitance and having an access circuit terminal. The memory cell further includes a voltage control unit to adjust a potential at said access circuit terminal in a retention state such that a retention time of the memory cell is increased. A method of operating a memory cell includes, for example, adjusting a potential at an access circuit terminal of the memory cell to increase a retention time.

Abstract: A bit line dummy core-cell comprises at least a first inverter and at least a second inverter which are cross coupled to form a bistable flip-flop. The first inverter comprises a first PMOS transistor and a first NMOS transistor connected in series by means of a first internal storage node between a high reference potential and a low reference potential. The second inverter comprises a second PMOS transistor and a second NMOS transistor connected in series by means of a second internal storage node. The source of the second PMOS transistor and the second internal storage node are connected to the low reference potential so that the first internal storage node always stores a logic high level. A first access transistor is coupled between a dummy bit line providing a self-timing signal and the first internal node storing the logical high level.

Abstract: The invention relates to a semiconductor circuit arrangement having a semiconductor substrate, a first doping region, a second doping region, a connection doping region, an insulation layer and an electrically conductive structure which is to be planarized, it being possible for the charge carriers formed during a planarization step to be reliably dissipated, and for dendrite formation to be prevented, by a discharge doping region formed in the first and second doping regions.

Abstract: A memory cell includes diffusion regions formed in a substrate. Each of the diffusion regions extends along a vertical direction in a layout view at a substrate level. A first gate electrode structure at a gate electrode level is generally dogleg shaped. The first gate electrode structure extends in an oblique direction, turns to a horizontal direction, extends over and crosses the diffusion regions in the horizontal direction. A first contact structure at a contact level is generally rectangular shaped in the layout view of the cell. The first contact structure electrically connects a first source/drain region of the first diffusion region to the first gate electrode structure and the first source/drain region of the second diffusion region. The first contact structure extends from the first source/drain region of the first diffusion region to the first source/drain region of the second diffusion region at the contact level.

Abstract: A bit line dummy core-cell comprises at least a first inverter and at least a second inverter which are cross coupled to form a bistable flip-flop. The first inverter comprises a first PMOS transistor and a first NMOS transistor connected in series by means of a first internal storage node between a high reference potential and a low reference potential. The second inverter comprises a second PMOS transistor and a second NMOS transistor connected in series by means of a second internal storage node. The source of the second PMOS transistor and the second internal storage node are connected to the low reference potential so that the first internal storage node always stores a logic high level. A first access transistor is coupled between a dummy bit line providing a self-timing signal and the first internal node storing the logical high level.

Abstract: An SRAM includes an SRAM cell with a semiconductor substrate material, and a capacitor. The capacitor includes a first electrode adjacent the substrate material, a thin oxide adjacent the first electrode and a second electrode adjacent the thin oxide.

Abstract: The invention relates to a ROM memory cell of a ROM memory, which provides a first predetermined potential or a second predetermined potential in the driven state at a memory cell output in a manner dependent on the programming state of the ROM memory cell.

Abstract: A semiconductor memory cell and an associated fabrication method are provided in which a storage capacitor is connected to a selection transistor. The storage capacitor is formed in a trench of a semiconductor substrate. At the trench surface, a capacitor dielectric and an electrically conductive filling layer are formed thereon for realization of a capacitor counterelectrode. The filling layer has a projection that extends outside the trench as far as the drain region and is electrically connected thereto.

Abstract: A memory cell includes transistors and two read ports. Each read port is configured to be connected to a read line. The memory cell is configured such that in a read operation of the memory cell an information stored in the memory cell is readable by a differential reading including an evaluation of an electric current between the two read ports.

Abstract: A semiconductor memory cell and production method provides a storage capacitor connected to a selection transistor. The storage capacitor is formed as a contact hole capacitor in at least one contact hole for a source or drain region. Such a semiconductor memory cell can be produced cost-effectively and allows a high integration density.

Abstract: A read-only memory arrangement and method for programming the memory arrangement are provided. The memory arrangement includes memory cells, which each have a transistor with two contacts and a control terminal, address lines, bit lines and a potential line. A combination of one of the address lines and one of the bit lines is uniquely assigned to each memory cell. The control terminal of each transistor is connected to the address line assigned to the respective memory cell. To program a memory cell into a first memory state, one of the contacts of the transistor of the memory cell is connected to the assigned bit line and the other of the contacts is connected to the potential line. To program a memory cell into a second memory state, no connections are established between the contacts of the transistor and either the assigned bit line or the potential line.

Abstract: A memory cell having three transistors and a capacitor having metallic electrodes is described. Multiple memory cells may be arranged in a memory unit or array. Collective electrodes may be used in a space-saving embodiment of the capacitor.

Abstract: The invention relates to a ROM memory cell of a ROM memory, which provides a first predetermined potential or a second predetermined potential in the driven state at a memory cell output in a manner dependent on the programming state of the ROM memory cell.

Abstract: A read-only memory arrangement and method for programming the memory arrangement are provided. The memory arrangement includes memory cells, which each have a transistor with two contacts and a control terminal, address lines, bit lines and a potential line. A combination of one of the address lines and one of the bit lines is uniquely assigned to each memory cell. The control terminal of each transistor is connected to the address line assigned to the respective memory cell. To program a memory cell into a first memory state, one of the contacts of the transistor of the memory cell is connected to the assigned bit line and the other of the contacts is connected to the potential line. To program a memory cell into a second memory state, no connections are established between the contacts of the transistor and either the assigned bit line or the potential line.

Abstract: The invention relates to a semiconductor circuit arrangement having a semiconductor substrate, a first doping region, a second doping region, a connection doping region, an insulation layer and an electrically conductive structure which is to be planarized, it being possible for the charge carriers formed during a planarization step to be reliably dissipated, and for dendrite formation to be prevented, by a discharge doping region formed in the first and second doping regions.

Abstract: A semiconductor memory cell and an associated fabrication method are provided in which a storage capacitor is connected to a selection transistor. The storage capacitor is formed in a trench of a semiconductor substrate. At the trench surface, a capacitor dielectric and an electrically conductive filling layer are formed thereon for realization of a capacitor counterelectrode. The filling layer has a projection that extends outside the trench as far as the drain region and is electrically connected thereto.

Abstract: A semiconductor memory component such as a mask-programmable ROM component, has two memory cell transistors adjacent to each other in one column of a memory cell field. First and a second row-select/potential-equalization lines are equidistant from the two memory cell transistors and vertically above a diffusion region, which is assigned to both memory cell transistors. The first or the second row-select/potential-equalization line can be connected both to the word line of the first memory cell transistor and to the word line of the memory cell transistor of the second memory cell for equalizing the potential with one of the two word lines.

Abstract: A semiconductor memory component such as a mask-programmable ROM component, has two memory cell transistors adjacent to each other in one column of a memory cell field. First and a second row-select/potential-equalization lines are equidistant from the two memory cell transistors and vertically above a diffusion region, which is assigned to both memory cell transistors. The first or the second row-select/potential-equalization line can be connected both to the word line of the first memory cell transistor and to the word line of the memory cell transistor of the second memory cell for equalizing the potential with one of the two word lines.