Patents by Inventor Martin Patterson

Martin Patterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110145479
    Abstract: A multi-tiered cache manager and methods for managing multi-tiered cache are described. Multi-tiered cache manager causes cached data to be initially stored in the RAM elements and selects portions of the cached data stored in the RAM elements to be moved to the flash elements. Each flash element is organized as a plurality of write blocks having a block size and wherein a predefined maximum number of writes is permitted to each write block. The portions of the cached data may be selected based on a maximum write rate calculated from the maximum number of writes allowed for the flash device and a specified lifetime of the cache system.
    Type: Application
    Filed: December 31, 2009
    Publication date: June 16, 2011
    Applicant: Gear Six, Inc.
    Inventors: Nisha TALAGALA, Berry Kercheval, Martin Patterson, Edward Pernicka, James Bowen
  • Patent number: 7932119
    Abstract: A method is provided for detecting laser optical paths in integrated circuit (IC) packages. The method provides an IC die encapsulated as a package in a compound of glass spheres and epoxy. Power is supplied to the IC. The IC is scanned with a laser. Typically, a laser wavelength is used that is minimally absorbed by the glass spheres in the epoxy compound of the IC package, and changes in current to the IC are detected. A detected current change is cross-referenced against a scanned IC package surface region. This process identifies an optical pathway underlying the scanned IC package surface region. In some aspects, this process leads to the identification of a glass sphere-collecting package structure underlying the optical pathway. Examples of a glass sphere-collecting structure might include an inner lead wire, lead frame edge, or die edge.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: April 26, 2011
    Assignee: Applied Micro Circuits Corporation
    Inventor: Joseph Martin Patterson
  • Patent number: 7931849
    Abstract: A method is provided for laser optically marking integrated circuit (IC) packages in a non-destructive manner. The method provides an IC die encapsulated as a package in a compound of glass spheres and epoxy. An acute angle is defined between a laser optical path and an IC package planar surface. The IC package surface is scanned with a laser, and in response to ablating the IC package surface, a legible mark on the planar surface.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: April 26, 2011
    Assignee: Applied Micro Circuits Corporation
    Inventor: Joseph Martin Patterson
  • Patent number: 7916397
    Abstract: An optical fiber micro array lens is provided along with an associated fabrication method. The micro array lens is fabricated from a mesh of optical fibers. The mesh includes a first plurality of cylindrical optical fibers. Each fiber from the first plurality has a flat bottom surface and a hemicylindrical top surface. The top and bottom surfaces are aligned in parallel with a central fiber axis. The mesh also includes a second plurality of cylindrical optical fibers. Each fiber from the second plurality has a hemicylindrical bottom surface overlying and in contact with the top surfaces of the first plurality of optical fibers, and a flat top surface. The top and bottom surfaces are aligned in parallel with a central fiber axis. Each contact of the first and second plurality of optical fibers forms a lens assembly in a micro array of lenses.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: March 29, 2011
    Assignee: Applied Micro Circuits Corporation
    Inventor: Joseph Martin Patterson
  • Publication number: 20110031993
    Abstract: A curve tracer signal conversion device is provided. The signal conversion device has an input connected to the curve tracer base port to accept a repeating sequence of stepped base signals. The conversion device has a signal input connected to either the curve tracer collector or emitter port, typically the collector. The conversion device has a plurality of signal outputs, where each signal output is sequentially connected to the selected (i.e. collector) curve tracer port in response to a corresponding base step signal. The signals outputs may be provided to a test fixture, for testing a multi-pin integrated circuit (IC).
    Type: Application
    Filed: August 31, 2009
    Publication date: February 10, 2011
    Inventor: Joseph Martin Patterson
  • Patent number: 7877490
    Abstract: A method for efficient communications with a cluster-based architecture preserves various aspects of integrity throughout one or more connections with a client, even in the midst of connection migration between nodes in the cluster. According to one aspect, the invention provides a mechanism for preventing the loss of packets arising from a TCP connection migration within the cluster. According to another aspect, the invention provides a mechanism for uniquely identifying conflicting TCP connections migrated to a common node. According to a still further aspect, the invention provides a distributed TCP timestamp mechanism so that the sender and receiver will have a consistent view of the timestamp even when each node has different local clock values and regardless of how many times the socket has been migrated.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: January 25, 2011
    Assignee: Violin Memory, Inc.
    Inventors: Nisha Talagala, Qing Huang, Rama Chitta, Martin Patterson
  • Publication number: 20100327875
    Abstract: A system and method are provided for testing an integrated circuit (IC) using thermally induced noise analysis. The method provides an IC die and supplies electrical power to the IC die. The IC die surface is scanned with a laser, and the laser beam irradiated locations on the IC die surface are tracked. The laser scanning heats active electrical elements underlying the scanned IC die surface. A frequency response of an IC die electrical interface is measured and correlated to irradiated locations. IC die defect regions are determined in response to identifying location-correlated frequency measurements exceeding a noise threshold. For example, a frequency measurement may be correlated to a die surface location, and if frequency measurement exceeds the noise threshold, then circuitry underlying that surface area may be identified as defective. Typically, die defect regions are associated with measurements in the frequency range between about 1 Hertz and 10 kilohertz.
    Type: Application
    Filed: June 24, 2009
    Publication date: December 30, 2010
    Inventor: Joseph Martin Patterson
  • Publication number: 20100289488
    Abstract: System and methods are provided for optical-magnetic Kerr effect signal analysis. In one aspect, a test fixture is supplied having parallel conductive lines, with an input of a first line adjacent a resistively loaded output of a second line and a resistively loaded output of the first line adjacent an input of the second line. An optically transparent test region is interposed between the conductive lines, and a metallic reflector underlies the test region. A signal reference is supplied to the input of the first line and a signal under test is supplied to the input of the second line. A light beam having a first angle of polarization is focused through the test region onto the reflector. The intensity of the reflected light is measured and the similarity between the signal under test and the reference signal can be determined in response to the measured light intensity.
    Type: Application
    Filed: May 14, 2009
    Publication date: November 18, 2010
    Inventor: Joseph Martin Patterson
  • Publication number: 20100277221
    Abstract: A method is provided for thermal electric binary logic control. The method accepts an input voltage representing an input logic state. A heat reference is controlled in response to the input voltage. The method supplies an output voltage representing an output logic state, responsive to the heat reference. More explicitly, the heat reference controls the output voltage of a temperature-sensitive voltage divider. For example, the temperature-sensitive voltage divider may be a thermistor voltage divider.
    Type: Application
    Filed: July 2, 2010
    Publication date: November 4, 2010
    Inventor: Joseph Martin Patterson
  • Publication number: 20100259831
    Abstract: An optical fiber micro array lens is provided along with an associated fabrication method. The micro array lens is fabricated from a mesh of optical fibers. The mesh includes a first plurality of cylindrical optical fibers. Each fiber from the first plurality has a flat bottom surface and a hemicylindrical top surface. The top and bottom surfaces are aligned in parallel with a central fiber axis. The mesh also includes a second plurality of cylindrical optical fibers. Each fiber from the second plurality has a hemicylindrical bottom surface overlying and in contact with the top surfaces of the first plurality of optical fibers, and a flat top surface. The top and bottom surfaces are aligned in parallel with a central fiber axis. Each contact of the first and second plurality of optical fibers forms a lens assembly in a micro array of lenses.
    Type: Application
    Filed: June 23, 2010
    Publication date: October 14, 2010
    Inventor: Joseph Martin Patterson
  • Patent number: 7772873
    Abstract: A method is provided for thermal electric binary logic control. The method accepts an input voltage representing an input logic state. A heat reference is controlled in response to the input voltage. The method supplies an output voltage representing an output logic state, responsive to the heat reference. More explicitly, the heat reference controls the output voltage of a temperature-sensitive voltage divider. For example, the temperature-sensitive voltage divider may be a thermistor voltage divider.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: August 10, 2010
    Assignee: Applied Micro Circuits Corporation
    Inventor: Joseph Martin Patterson
  • Patent number: 7768283
    Abstract: A universal socketless integrated circuit (IC) electrical test fixture is provided. The test fixture is made up of a probing platform to accept and heatsink an IC. The IC has electrical contacts formed on a bottom surface in an array of m rows, where each row includes n, or less contacts. A probe arm includes p probe pins, where p is greater than, or equal to n. A clamping mechanism mechanically interfaces the probe arm probe pins to a row of IC contacts under test. An electrical measurement device has a first interface connected to the p probe pins of the probe arm to measure electrical characteristics associated with the IC contacts under test. The probe arm, clamping mechanism, and probe platform work in cooperation to electrically interface any row of the IC contacts with the electrical measurement device.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: August 3, 2010
    Assignee: Applied Micro Circuits Corporation
    Inventor: Joseph Martin Patterson
  • Patent number: 7768706
    Abstract: An optical fiber micro array lens is provided along with an associated fabrication method. The micro array lens is fabricated from a mesh of optical fibers. The mesh includes a first plurality of cylindrical optical fibers. Each fiber from the first plurality has a flat bottom surface and a hemicylindrical top surface. The top and bottom surfaces are aligned in parallel with a central fiber axis. The mesh also includes a second plurality of cylindrical optical fibers. Each fiber from the second plurality has a hemicylindrical bottom surface overlying and in contact with the top surfaces of the first plurality of optical fibers, and a flat top surface. The top and bottom surfaces are aligned in parallel with a central fiber axis. Each contact of the first and second plurality of optical fibers forms a lens assembly in a micro array of lenses.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: August 3, 2010
    Assignee: Applied Micro Circuits Corporation
    Inventor: Joseph Martin Patterson
  • Patent number: 7768338
    Abstract: A method is provided for the electronic processing of analog signals in thermaltronic device. The method accepts an analog input signal, e.g., an AC signal, at a thermaltronic device input and generates a thermal electric (TE) temperature having a first transfer function responsive to the input signal. As opposed to having a digital response, the transfer function is either linear or logarithmic. An analog output signal, e.g., an AC signal, is generated having a second transfer function responsive to the TE, which is likewise either linear or logarithmic.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: August 3, 2010
    Assignee: Applied Micro Circuits Corporation
    Inventor: Joseph Martin Patterson
  • Publication number: 20100177405
    Abstract: An optical fiber micro array lens is provided along with an associated fabrication method. The micro array lens is fabricated from a mesh of optical fibers. The mesh includes a first plurality of cylindrical optical fibers. Each fiber from the first plurality has a flat bottom surface and a hemicylindrical top surface. The top and bottom surfaces are aligned in parallel with a central fiber axis. The mesh also includes a second plurality of cylindrical optical fibers. Each fiber from the second plurality has a hemicylindrical bottom surface overlying and in contact with the top surfaces of the first plurality of optical fibers, and a flat top surface. The top and bottom surfaces are aligned in parallel with a central fiber axis. Each contact of the first and second plurality of optical fibers forms a lens assembly in a micro array of lenses.
    Type: Application
    Filed: January 13, 2009
    Publication date: July 15, 2010
    Inventor: Joseph Martin Patterson
  • Patent number: 7703102
    Abstract: An approach for allocating resources to an apparatus based on preemptable resource requirements generally involves a resource allocator determining that a resource that satisfies a resource requirement for one apparatus is not available but that another resource that currently satisfies another resource requirement for another apparatus does satisfy the resource requirement. The resource allocator determines that the other resource requirement for the other apparatus is characterized in that resources that currently satisfy the other resource requirement may be de-allocated from the other apparatus, such as a preemptable resource requirement. The resource allocator de-allocates the resource from the other apparatus and allocates the resource to the one apparatus. A preemptable resource requirement can be based on a suspendable resource requirement or a set of alternative resource requirements.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: April 20, 2010
    Assignee: Oracle America, Inc.
    Inventors: Christopher M. Eppstein, Ashar Aziz, Thomas Markson, Martin Patterson
  • Patent number: 7659750
    Abstract: A thermal electric (TE) binary NOR gate logic circuit is provided with a method for NOR logic gating. The method accepts a first input voltage representing an input binary logic state and generates a first thermal electric (TE) temperature in response to the first input voltage. A second input voltage is accepted representing an input binary logic state, and a second TE temperature is generated in response to the second input voltage. In response to the first and second TE temperatures, a NOR logic state output voltage is generated. More explicitly, a first control voltage is generated in response to the first TE temperature, and a second control voltage is generated in response to the second TE temperature. Then, a third TE temperature is generated in response to the first and second control voltages, which in turn generates the output voltage.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: February 9, 2010
    Assignee: Applied Micro Circuits Corporation
    Inventor: Joseph Martin Patterson
  • Patent number: 7657615
    Abstract: An approach for provisioning network devices generally involves supplying boot data to network devices over a network so that the network devices can be booted up in an imaging mode or an application mode, depending upon the particular boot data supplied to the network device. When booted up in the imaging mode, imaging data can be downloaded and stored on network devices. When booted up in the application mode, the network devices execute one or more programs contained in the image data stored on the network devices. The first and second boot data may be in the form of boot loader scripts. Furthermore, the first and second boot data may be provided to the network device in the payload of a dynamic host configuration protocol (DHCP) reply. The DHCP reply may be generated and provided by a DHCP server to the network device in response to receiving a DHCP request from the network device. The approach may be implemented using a secure network environment.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: February 2, 2010
    Assignee: Sun Microsystems, Inc.
    Inventors: Martin Patterson, Jayaraman Manni, Shriram Krishnan, Benjamin H. Stoltz, Christopher T. La
  • Publication number: 20090323287
    Abstract: A fixture and method are provided for cooling an IC in the performance of focused beam processes. The method provides a holding/cooling fixture with thermal electric (TE) jaws having an IC interface surface and a heatsink interface. An IC die is secured between the IC interface surfaces of the jaws. Electrical energy is supplied to the TE jaws, creating a negative temperature differential between the IC interface and heatsink interfaces. As a result, the IC die is cooled. A focused beam is applied to a local region of the IC die. Some examples of the focused beam include a focused ion beam (FIB), scanning electron microscope (SEM), E-beam, or a laser scanning microscope (LSM). The focused beam heats the local region of the IC, while the bulk of the IC remains cooled. Typically, each TE jaw includes a plurality of TE elements thermally connected in series.
    Type: Application
    Filed: December 8, 2008
    Publication date: December 31, 2009
    Inventor: Joseph Martin Patterson
  • Publication number: 20090322343
    Abstract: A reflector tool and a method are provided for three-dimensional integrated circuit (IC) failure analysis. An IC (die) has top and bottom surfaces, a perimeter, and a first side. The IC is electrically connected to a current sensing amplifier. The first side of the IC is scanned in the X plane with an infrared laser beam while changes in IC current flow are sensed. The sensed current changes are cross-referenced to the location of the infrared laser beam in the X plane. In one aspect, a plurality of scans are performed on the first side in the X plane, with at a corresponding plurality of steps in the Y plane, so that current changes can be cross-referenced to locations in the X and Y planes. Using this 2-D analysis through the IC side, a human operator or software program can determine defects in the IC.
    Type: Application
    Filed: February 18, 2009
    Publication date: December 31, 2009
    Inventor: Joseph Martin Patterson