Patents by Inventor Martin Patterson

Martin Patterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090325322
    Abstract: A method is provided for laser optically marking integrated circuit (IC) packages in a non-destructive manner. The method provides an IC die encapsulated as a package in a compound of glass spheres and epoxy. An acute angle is defined between a laser optical path and an IC package planar surface. The IC package surface is scanned with a laser, and in response to ablating the IC package surface, a legible mark on the planar surface.
    Type: Application
    Filed: September 30, 2008
    Publication date: December 31, 2009
    Inventor: Joseph Martin Patterson
  • Publication number: 20090325325
    Abstract: A method is provided for detecting laser optical paths in integrated circuit (IC) packages. The method provides an IC die encapsulated as a package in a compound of glass spheres and epoxy. Power is supplied to the IC. The IC is scanned with a laser. Typically, a laser wavelength is used that is minimally absorbed by the glass spheres in the epoxy compound of the IC package, and changes in current to the IC are detected. A detected current change is cross-referenced against a scanned IC package surface region. This process identifies an optical pathway underlying the scanned IC package surface region. In some aspects, this process leads to the identification of a glass sphere-collecting package structure underlying the optical pathway. Examples of a glass sphere-collecting structure might include an inner lead wire, lead frame edge, or die edge.
    Type: Application
    Filed: June 25, 2008
    Publication date: December 31, 2009
    Inventor: Joesph Martin Patterson
  • Patent number: 7602218
    Abstract: A thermal electric (TE) binary NAND gate logic circuit is provided with a method for NAND logic gating. The method accepts a first input voltage representing an input binary logic state and generates a first thermal electric (TE) temperature in response to the first input voltage. A second input voltage is accepted representing an input binary logic state, and a second TE temperature is generated in response to the second input voltage. In response to the first and second TE temperatures, a NAND logic state output voltage is generated. More explicitly, a first control voltage is generated in response to the first TE temperature, and a second control voltage is generated in response to the second TE temperature. Then, a third TE temperature is generated in response to the first and second control voltages, which in turn generates the output voltage.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: October 13, 2009
    Assignee: Applied Micro Circuits Corporation
    Inventor: Joseph Martin Patterson
  • Publication number: 20090206907
    Abstract: A method is provided for the electronic processing of analog signals in thermaltronic device. The method accepts an analog input signal, e.g., an AC signal, at a thermaltronic device input and generates a thermal electric (TE) temperature having a first transfer function responsive to the input signal. As opposed to having a digital response, the transfer function is either linear or logarithmic. An analog output signal, e.g., an AC signal, is generated having a second transfer function responsive to the TE, which is likewise either linear or logarithmic.
    Type: Application
    Filed: September 24, 2008
    Publication date: August 20, 2009
    Inventor: Joseph Martin Patterson
  • Publication number: 20090206882
    Abstract: A thermal electric (TE) binary NOR gate logic circuit is provided with a method for NOR logic gating. The method accepts a first input voltage representing an input binary logic state and generates a first thermal electric (TE) temperature in response to the first input voltage. A second input voltage is accepted representing an input binary logic state, and a second TE temperature is generated in response to the second input voltage. In response to the first and second TE temperatures, a NOR logic state output voltage is generated. More explicitly, a first control voltage is generated in response to the first TE temperature, and a second control voltage is generated in response to the second TE temperature. Then, a third TE temperature is generated in response to the first and second control voltages, which in turn generates the output voltage.
    Type: Application
    Filed: May 13, 2008
    Publication date: August 20, 2009
    Inventor: Joesph Martin Patterson
  • Publication number: 20090206911
    Abstract: A method is provided for thermal electric binary logic control. The method accepts an input voltage representing an input logic state. A heat reference is controlled in response to the input voltage. The method supplies an output voltage representing an output logic state, responsive to the heat reference. More explicitly, the heat reference controls the output voltage of a temperature-sensitive voltage divider. For example, the temperature-sensitive voltage divider may be a thermistor voltage divider.
    Type: Application
    Filed: February 15, 2008
    Publication date: August 20, 2009
    Inventor: Joesph Martin Patterson
  • Publication number: 20090206883
    Abstract: A thermal electric (TE) binary NAND gate logic circuit is provided with a method for NAND logic gating. The method accepts a first input voltage representing an input binary logic state and generates a first thermal electric (TE) temperature in response to the first input voltage. A second input voltage is accepted representing an input binary logic state, and a second TE temperature is generated in response to the second input voltage. In response to the first and second TE temperatures, a NAND logic state output voltage is generated. More explicitly, a first control voltage is generated in response to the first TE temperature, and a second control voltage is generated in response to the second TE temperature. Then, a third TE temperature is generated in response to the first and second control voltages, which in turn generates the output voltage.
    Type: Application
    Filed: November 13, 2008
    Publication date: August 20, 2009
    Inventor: Joseph Martin Patterson
  • Patent number: 7565446
    Abstract: The present invention relates generally to a method for efficient I/O handling in a cluster-based architecture. According to one aspect, the invention enables efficient scheduling of TCP connection migrations within a cluster. According to another aspect, the invention enables I/Os performed as TCP handoff operations to coexist on the same TCP/IP connection with I/Os performed as remote operations.
    Type: Grant
    Filed: August 27, 2007
    Date of Patent: July 21, 2009
    Assignee: Gear Six, Inc.
    Inventors: Nisha Talagala, Martin Patterson
  • Patent number: 7564267
    Abstract: A thermal electric binary logic circuit is provided along with a method for switching a thermal electric binary logic circuit. The method accepts an input voltage representing an input logic state and generates a thermal electric (TE) temperature value in response to the input voltage. Then, in response to the TE temperature value, a TE voltage is generated and supplied as an output voltage representing an output logic state. In one aspect, a first TE element is connected to the input voltage and to a current source/sink having an intermediate voltage. As a result, the first TE element generates a first temperature reference. A second TE thermally is connected to the first TE, electrically connected to a first voltage reference, and electrically connected to an output to supply the output voltage. As a result, a first voltage varies across the second TE in response to the first temperature.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: July 21, 2009
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: Joseph Martin Patterson
  • Patent number: 7503045
    Abstract: Methods and apparatus providing a dynamically sized, highly scalable and available server farm are disclosed. A Virtual Server Farm (VSF) is created out of a wide scale computing fabric (“Computing Grid”) which is physically constructed once and then logically divided up into VSFs for various organizations on demand. Each organization retains independent administrative control of a VSF. A VSF is dynamically firewalled within the Computing Grid. Allocation and control of the elements and topology in the VSF is performed by a Control Plane connected to all computing, networking, and storage elements in the computing grid through special control ports. No physical rewiring is necessary in order to construct VSFs in many different configurations, including single-tier Web server or multi-tier Web-server, application server, database server configurations.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: March 10, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Ashar Aziz, Tom Markson, Martin Patterson
  • Publication number: 20090059862
    Abstract: The present invention relates generally to a method for efficient I/O handling in a cluster-based architecture. According to one aspect, the invention enables efficient scheduling of TCP connection migrations within a cluster. According to another aspect, the invention enables I/Os performed as TCP handoff operations to coexist on the same TCP/IP connection with I/Os performed as remote operations.
    Type: Application
    Filed: August 27, 2007
    Publication date: March 5, 2009
    Inventors: Nisha Talagala, Martin Patterson
  • Patent number: 7463648
    Abstract: An approach for allocating resources to an apparatus based on resource requirements generally involves a resource allocator receiving a request that specifies resource requirements for the apparatus. A resource allocator determines whether resources are available that satisfy the resource requirements. If resources are available that satisfy a resource requirement, the resource allocator indicates that the resource requirement is fulfilled and the resources are allocated to the apparatus. If resources are not available that satisfy a resource requirement, the resource allocator indicates that the resource requirement is not fulfilled and the resources are not allocated to the apparatus. The apparatus is implemented based on the allocated resources. A resource requirement can be optional so that if the optional resource requirement is not fulfilled, the apparatus can still be implemented.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: December 9, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: Christopher M. Eppstein, Ashar Aziz, Thomas Markson, Martin Patterson
  • Patent number: 7370013
    Abstract: A novel approach for determining an amount to be billed to a customer for the use of resources is based upon usage data and value data. The usage data indicates usage, by the customer, of a set of one or more resources during a specified period of time. The set of one or more resources may be dynamically selected and de-selected from a plurality of resources at any time. For example, the set of one or more resources may comprise a VSF as described herein. The value data indicates generally value provided by each resource from the set of one or more resources used during the specified period of time. The value provided by each resource may be expressed in service units per unit time and a charge may be applied for each service unit consumed during a specified period of time. Example billing schemes to which the approach is applicable include, without limitation, basic billing, flex billing, event flex billing and open flex billing.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: May 6, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: Ashar Aziz, Thomas Markson, Martin Patterson, Mark Gray, Christopher J. Conway, Patrick A Tickle
  • Publication number: 20070266108
    Abstract: A method and apparatus of providing high performance and highly scalable storage acceleration includes a cluster node-spanning RAM disk (CRD) interposed in the data path between a storage server and a computer server. The CRD addresses performance problems with applications that need to access large amounts of data and are negatively impacted by the latency of classic disk-based storage systems. It solves this problem by placing the data the application needs into a large (with respect to the server's main memory) RAM-based cache where it can be accessed with extremely low latency, hence improving the performance of the application significantly. The CRD is implemented using a novel architecture which has very significant cost and performance advantages over existing or alternative solutions.
    Type: Application
    Filed: February 28, 2006
    Publication date: November 15, 2007
    Inventors: Martin Patterson, Matthias Oberdorfer
  • Patent number: 7237077
    Abstract: A method and apparatus for replicating an image from a source to a destination disk are provided. Specific embodiments may be optimized for single source to multiple destination replication requests, for example. In one embodiment, the present invention provides tools and techniques for synchronous data replication responsive to asynchronous same-source-to-different-destination replication requests.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: June 26, 2007
    Assignee: Sun Microsystems, Inc.
    Inventors: Martin Patterson, Shriram Krishnan, Jayaraman Manni, Benjamin H. Stoltz
  • Patent number: 7146233
    Abstract: Methods and apparatus providing, controlling and managing a dynamically sized, highly scalable and available server farm are disclosed. A Virtual Server Farm (VSF) is created out of a wide scale computing fabric (“Computing Grid”) which is physically constructed once and then logically divided up into VSFs for various organizations on demand. Each organization retains independent administrative control of a VSF. A VSF is dynamically firewalled within the Computing Grid. Allocation and control of the elements in the VSF is performed by a control plane connected to all computing, networking, and storage elements in the computing grid through special control ports. The internal topology of each VSF is under control of the control plane. A request queue architecture is also provided for processing work requests that allows selected requests to be blocked until required human intervention is satisfied.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: December 5, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Ashar Aziz, Thomas Markson, Martin Patterson, Mark Gray, Osman Ismael
  • Patent number: 7093005
    Abstract: A method and apparatus for defining and deploying a networked computer system features creating and storing a graphical representation using a graphical editor to drag and drop icons representing computing elements and network elements into a workspace, such that a logical configuration of the networked computer system is represented by the graphical representation. A corresponding textual representation of the computer system is automatically created and stored according to a structured markup language. Based on the textual representation, one or more commands are generated for configuring an operable computer system that conforms to the logical configuration. The commands may be directed to one or more devices that are interconnected to one or more computing elements and storage devices, to instruct the devices to logically connect the computing elements and storage devices into the computer system.
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: August 15, 2006
    Assignee: Terraspring, Inc.
    Inventor: Martin Patterson
  • Patent number: 7036124
    Abstract: Resource management for controlling allocation of a resource to competing computer processes is achieved through the use of a joining function. A resource manager is responsive to identification of a thread for a first process requesting allocation of the resource, when the resource is already allocated to a thread for a second process, to establish a joining function to the thread for the second process. The joining function is operable to notify the resource manager on termination of the thread for the second process. The resource manager can therefore be operable in response to termination of the thread for the second process to allocate the resource to the first process. The first and second processes can be call handling processes for telecommunications apparatus where the resource manager provides allocation of a telephony resource, such as a modem or network interface, to the competing call handling applications. A telephony interface and the applications can be implemented in the Java™ language.
    Type: Grant
    Filed: March 1, 1999
    Date of Patent: April 25, 2006
    Assignee: Sun Microsystems, Inc.
    Inventor: David John Martin Patterson
  • Patent number: 6779016
    Abstract: Methods and apparatus providing a dynamically sized, highly scalable and available server farm are disclosed. A Virtual Server Farm (VSF) is created out of a wide scale computing fabric (“Computing Grid”) which is physically constructed once and then logically divided up into VSFs for various organizations on demand. Each organization retains independent administrative control of a VSF. A VSF is dynamically firewalled within the Computing Grid. A allocation and control of the elements in the VSF is performed by a Control Plane connected to all computing, networking, and storage elements in the computing grid through special control ports. The internal topology of each VSF is under control of the Control Plane. No physical rewiring is necessary in order to construct VSFs in many different configurations, including single-tier Web server or multi-tier Web-server, application server, database server configurations. Each tier of a multi-tier VSF (e.g.
    Type: Grant
    Filed: February 11, 2000
    Date of Patent: August 17, 2004
    Assignee: Terraspring, Inc.
    Inventors: Ashar Aziz, Tom Markson, Martin Patterson
  • Patent number: RE39360
    Abstract: A system for automatically encrypting and decrypting data packet sent from a source host to a destination host across a public internetwork. A tunnelling bridge is positioned at each network, and intercepts all packets transmitted to or from its associated network. The tunnelling bridge includes tables indicated pairs of hosts or pairs of networks between which packets should be encrypted. When a packet is transmitted from a first host, the tunnelling bridge of that host's network intercepts the packet, and determines from its header information whether packets from that host that are directed to the specified destination host should be encrypted; or, alternatively, whether packets from the source host's network that are directed to the destination host's network should be encrypted.
    Type: Grant
    Filed: August 19, 1998
    Date of Patent: October 17, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Ashar Aziz, Geoffrey Mulligan, Martin Patterson, Glenn Scott