Abstract: The present invention provides a method of manufacturing an integrated circuit comprising the steps of: providing a semiconductor substrate, etching at least one trench into a surface of said semiconductor substrate, performing an ion implantation step, wherein a direction of said ion implantation step is parallel to a vertical centre line of said trench, and performing a single oxidation step to form a first oxide layer with a first layer thickness covering a bottom of said at least one trench and a second oxide layer with a second layer thickness covering the sidewalls of said at least one trench, wherein said first layer thickness differs from said second layer thickness.

Abstract: An integrated circuit is disclosed. One embodiment provides a field-effect transistor including a gate electrode, a channel region and a first source/drain region. The gate electrode may include a main section determining a first flat band voltage between the gate electrode and the channel region and a first lateral section that is in contact with the main section and that determines a second flat band voltage between the gate electrode and the first source/drain region. The first and second flat band voltages differ by at least 0.1 eV.

Abstract: An integrated circuit having a memory cell array and a method of forming an integrated circuit is disclosed. One embodiment provides bitlines running along a first direction, wordlines running along a second direction substantially perpendicular to the first direction, active areas and bitline contacts. The bitline contacts are arranged in columns extending in the second direction and in rows extending in the first direction. A distance between neighboring bitlines is DL, and a distance between neighboring bitline contacts is DC, DC being measured parallel to the first direction. The following relation holds: 1/2.25?DL/DC?1/1.75.

Abstract: The invention concerns a structure comprising a first and a second component and a connecting element which connects the two components and which has at least two spring elements. In order to provide a structure and in particular an optical structure of the above-mentioned kind in which the two components have an extremely high level of positional and angular accuracy relative to each other even with major fluctuations in temperature it is proposed according to the invention that each spring element has a spring constant at least twice as great in two respective mutually perpendicular spatial directions as in the third spatial direction perpendicular to the first two spatial directions, referred to as the elasticity direction, wherein the two spring elements have elasticity directions which do not extend parallel to each other.

Abstract: An integrated circuit having a memory arrangement including capacitor elements and further capacitor elements is disclosed. One embodiment provides a substrate layer with contact pads and further contact pads; the capacitor elements being disposed in a first level on the substrate layer and connected with the contact pads; the further capacitor elements being disposed in a second level above the first level; contact elements being disposed between the capacitor elements and connected with the further contact pads; the further capacitor elements being disposed above the contact elements and being connected with the contact elements.

Abstract: A memory cell array having a plurality of memory cells is disclosed. In one embodiment, each memory cell includes a storage capacitor and an access transistor, a plurality of bit lines orientated in a first direction, a plurality of word lines orientated in a second direction, the second direction being perpendicular to the first direction, a semiconductor substrate with a surface, a plurality of active areas being formed in the semiconductor substrate, each active area extending in the second direction, the access transistors being partially formed in the active areas and electrically coupling corresponding ones of the storage capacitors to corresponding bit lines, wherein a gate electrode of each of the access transistors is connected with a corresponding word line, a capacitor dielectric of the storage capacitor has a relative dielectric constant of more than 8, and the word lines are disposed above the bit lines.

Abstract: An integrated circuit includes a memory cell array comprising memory cells with a transistor. The transistors are formed in active areas. The memory cell array further includes bit lines oriented in a first direction and word lines oriented in a second direction. The active areas extend in the second direction. The bottom side of each gate electrode of the transistors is disposed under the bottom side of each word line. In addition, the word lines are disposed over the bit lines.

Abstract: Fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected thereto on one side through a buried contact, in particular, for a semiconductor memory cell with a planar selection transistor in the substrate and connected through the buried contact, includes providing a trench using an opening in a hard mask, providing a capacitor dielectric in lower and central trench regions, the collar in central and upper trench regions, and a conductive filling at least as far as the insulation collar topside, completely filling the trench with a filling material, carrying out STI trench fabrication process, removing the filling material and sinking the filling to below the collar topside, forming an insulation region on one side above the collar; uncovering a connection region on a different side above the collar, and forming the buried contact by depositing and etching back a metallic filling.

Abstract: A memory cell array includes memory cells with storage capacitor and an access transistor. The access transistors are formed in active areas. The memory cell array further includes bit lines oriented in a first direction and word lines oriented in a second direction. The active areas extend in the second direction. The bottom side of each gate electrode of the transistors is disposed beneath the bottom side of each word line. In addition, the word lines are disposed above the bit lines.

Abstract: A method of forming a doped semiconductor portion includes providing a semiconductor substrate with a surface, and providing protruding portions of a covering layer on the substrate surface, where the portions are arranged in a pattern of lines or segments of lines extending in a first direction. Portions of a resist layer are provided on the substrate surface, where the portions of the resist layer are arranged in a pattern of lines or segments of lines extending in a second direction, and the second direction intersects the first direction. The portions of the resist layer have a thickness d, the thickness d being measured perpendicularly with respect to the substrate surface. A tilted ion implantation step is then performed.

Abstract: One embodiment of the present invention relates to a transistor that is at least partially formed in a semiconductor substrate having a surface. In particular, the transistor includes a first source/drain region, a second source/drain region, a channel region connecting said first and second source/drain regions. Said channel region is disposed in said semiconductor substrate. A channel direction is defined by a line connecting said first and said second source/drain regions. A gate groove is formed in said semiconductor substrate. Said gate groove is formed adjacent to said channel region. Said gate groove includes an upper portion and a lower portion, said upper portion being adjacent to said lower portion, and a gate dielectric layer disposed between said channel region and said gate groove.

Abstract: Memory cells having trench capacitors, the trench capacitor being at least partially filled with a material which could not withstand high-temperature processes used during the fabrication of a memory chip without impairment of its electrical parameters. What is essential to the invention is that the material of the trench capacitor is introduced into the trench after the high-temperature processes. The method according to the invention makes it possible to use dielectric layers having large dielectric constants and electrode layers made of metallic material. The electrical properties of the trench capacitor are thus improved in comparison with known trench capacitors.

Abstract: In a method for producing a trench transistor, a substrate of a first conduction type is provided and a trench in the substrate and a gate dielectric in the trench are formed. A first conductive filling in the trench as a gate electrode on the gate dielectric and first source and drain regions are formed. An etched-back first conductive filling is produced by etching back the first conductive filling down to a depth below the first source and drain regions and second source and drain regions are formed. The second source and drain regions adjoin the first source and drain regions and extend to a depth at least as far as the etched-back first conductive filling. An insulation spacer above the etched-back first conductive filling is formed in the trench and a second conductive filling is provided in the trench as an upper part of the gate electrode.

Abstract: A connecting structure connects a storage electrode of a trench capacitor and a selection transistor that are at least partially formed in a semiconductor substrate. The connecting structure includes a portion of an intermediate layer disposed adjacent to a surface of the storage electrode, and an electrically conducting material disposed adjacent to the intermediate layer and electrically connected to a semiconductor substrate surface portion adjacent to the selection transistor, wherein a part of the connecting structure is disposed above the semiconductor substrate surface so as to be adjacent to a horizontal substrate surface portion.

Abstract: A method for manufacturing a surface strap connection between a trench capacitor and a selection transistor includes providing a masking material on a surface of a semiconductor substrate in areas where no trench capacitors have been formed. An undoped semiconductor layer having vertical and horizontal areas is applied. An oblique ion implantation is performed such that a vertical area of the semiconductor layer on which the connecting structure is to be formed is not doped. After removal of the undoped portion of the semiconductor layer, the exposed portion of the masking material is laterally etched, one part of the substrate surface is exposed, and the doped part of the semiconductor layer is removed. An electrically conducting connection material is applied so that an electrical contact exists between the exposed portion of the substrate surface and the storage electrode.

Abstract: A memory cell array includes memory cells with storage capacitor and an access transistor. The access transistors are formed in active areas. The memory cell array further includes bit lines oriented in a first direction and word lines oriented in a second direction. The active areas extend in the second direction. The bottom side of each gate electrode of the transistors is disposed beneath the bottom side of each word line. In addition, the word lines are disposed above the bit lines.

Abstract: Process for producing a plurality of gate stacks approximately the same height and equidistant on a semiconductor substrate. The process includes providing a gate dielectric on the semiconductor substrate and applying and patterning at least a first layer and a second layer, above the first layer, to the gate dielectric to produce the gate stacks. An oblique implantation of an oxidation-inhibiting implantation species is carried out into two opposite, uncovered side faces of the second of the gate stacks, with respectively adjacent gate stacks serving to shadow the uncovered side faces of the first layer of the gate stacks. Oxidation to simultaneously form a first oxide layer on uncovered side faces of the first layer of the gate stacks and a second oxide layer on uncovered side faces of the second layer of the gate stacks is carried out, the thickness of the first oxide layer being greater than the thickness of the second oxide layer.

Abstract: A transistor is provided which advantageously utilizes a part of the area which, in conventional transistors, is provided for the isolation between the transistors. In this case, the channel width can be enlarged in a self-aligned manner without the risk of short circuits. The field-effect transistor according to the invention has the advantage that it is possible to ensure a significant increase in the effective channel width for the forward current ION compared with previously used, conventional transistor structures, without having to accept a reduction of the integration density that can be attained. Thus, by way of example, the forward current ION can be increased by up to 50%, without having to alter the arrangement of the active regions or of the trench isolation.

Abstract: A transistor is provided which advantageously utilizes a part of the area which, in conventional transistors, is provided for the isolation between the transistors. In this case, the channel width can be enlarged in a self-aligned manner without the risk of short circuits. The field-effect transistor according to the invention has the advantage that it is possible to ensure a significant increase in the effective channel width for the forward current ION compared with previously used, conventional transistor structures, without having to accept a reduction of the integration density that can be attained. Thus, by way of example, the forward current ION can be increased by up to 50%, without having to alter the arrangement of the active regions or of the trench isolation.

Abstract: The invention relates to a field effect transistor in which the planar channel region on the upper surface of the elevation is extended in width by means of additional vertical channel regions on the lateral surfaces of the elevation. Said additional vertical channel regions connect directly to the planar channel region (vertical extended channel regions). Said field effect transistor has the advantage that a significant increase in the effective channel width for the current flow ION can be guaranteed relative to conventional transistor structures used up until the present, without having to accept a reduction in the achievable integration density. Said field effect transistor furthermore has a low reverse current IOFF. The above advantages are achieved without the thickness of the gate insulators up to the region of the charge transfer tunnels having to be reduced or a reduced stability.