Patents by Inventor Martin Saint-Laurent
Martin Saint-Laurent has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11347256Abstract: Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.Type: GrantFiled: January 6, 2021Date of Patent: May 31, 2022Assignee: QUALCOMM IncorporatedInventors: Martin Saint-Laurent, Lam Ho, Carlos Andres Rodriguez Ancer, Bhavin Shah
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Patent number: 11047946Abstract: Aspects of the disclosure are directed to voltage-based current sensing. In accordance with one aspect, voltage-based current sensing may include performing a coarse calibration of a voltage based current sensor to determine a coarse offset; performing a fine calibration of the voltage based current sensor to determine a fine offset; performing a frequency calibration of the voltage based current sensor to determine a frequency offset; and performing a transfer function calibration of the voltage based current sensor to determine a sensor transfer function using one or more of the coarse offset, the fine offset and the frequency offset; and measuring a load current using the sensor transfer function.Type: GrantFiled: May 8, 2018Date of Patent: June 29, 2021Assignee: Qualcomm IncorporatedInventors: Nam Dang, Rajeev Jain, Swarna Navubothu, Alan Lewis, Martin Saint-Laurent, Tung Nang Pham, Joseph Terregrossa, Paras Gupta, Somasekhar Maradani
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Publication number: 20210124387Abstract: Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.Type: ApplicationFiled: January 6, 2021Publication date: April 29, 2021Inventors: Martin SAINT-LAURENT, Lam HO, Carlos Andres RODRIGUEZ ANCER, Bhavin SHAH
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Patent number: 10890937Abstract: Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.Type: GrantFiled: November 16, 2018Date of Patent: January 12, 2021Assignee: Qualcomm IncorporatedInventors: Martin Saint-Laurent, Lam Ho, Carlos Andres Rodriguez Ancer, Bhavin Shah
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Publication number: 20190346528Abstract: Aspects of the disclosure are directed to voltage-based current sensing. In accordance with one aspect, voltage-based current sensing may include performing a coarse calibration of a voltage based current sensor to determine a coarse offset; performing a fine calibration of the voltage based current sensor to determine a fine offset; performing a frequency calibration of the voltage based current sensor to determine a frequency offset; and performing a transfer function calibration of the voltage based current sensor to determine a sensor transfer function using one or more of the coarse offset, the fine offset and the frequency offset; and measuring a load current using the sensor transfer function.Type: ApplicationFiled: May 8, 2018Publication date: November 14, 2019Inventors: Nam DANG, Rajeev JAIN, Swarna NAVUBOTHU, Alan LEWIS, Martin SAINT-LAURENT, Tung Nang PHAM, Joseph TERREGROSSA, Paras GUPTA, Somasekhar MARADANI
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Patent number: 10409317Abstract: Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.Type: GrantFiled: June 5, 2017Date of Patent: September 10, 2019Assignee: QUALCOMM IncorporatedInventors: Martin Saint-Laurent, Lam Ho, Carlos Andres Rodriguez Ancer, Bhavin Shah
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Patent number: 10309838Abstract: A temperature sensor position offset error correction power implementation include monitors (e.g., digital power monitor/meter) to measure activity on a die, and uses the activity measurements to compute real-time temperature offsets by converting activity to power, which can be used in a simplified compact thermal model. A system on chip including the die receives a temperature measurement of a region of the system on chip from a sensor. Power consumed by the region is estimated based on the measured activity, and temperature measurement of the system on chip is adjusted based on the estimated power.Type: GrantFiled: September 8, 2016Date of Patent: June 4, 2019Assignee: QUALCOMM IncorporatedInventors: Ali Akbar Merrikh, Martin Saint-Laurent, Mohammad Ghasemazar, Rajit Chandra, Mohamed Allam
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Publication number: 20190086946Abstract: Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.Type: ApplicationFiled: November 16, 2018Publication date: March 21, 2019Inventors: Martin SAINT-LAURENT, Lam HO, Carlos Andres RODRIGUEZ ANCER, Bhavin SHAH
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Publication number: 20180348809Abstract: Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.Type: ApplicationFiled: June 5, 2017Publication date: December 6, 2018Inventors: Martin Saint-Laurent, Lam Ho, Carlos Andres Rodriguez Ancer, Bhavin Shah
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Publication number: 20180066998Abstract: A temperature sensor position offset error correction power implementation include monitors (e.g., digital power monitor/meter) to measure activity on a die, and uses the activity measurements to compute real-time temperature offsets by converting activity to power, which can be used in a simplified compact thermal model. A system on chip including the die receives a temperature measurement of a region of the system on chip from a sensor. Power consumed by the region is estimated based on the measured activity, and temperature measurement of the system on chip is adjusted based on the estimated power.Type: ApplicationFiled: September 8, 2016Publication date: March 8, 2018Inventors: Ali Akbar MERRIKH, Martin SAINT-LAURENT, Mohammad GHASEMAZAR, Rajit CHANDRA, Mohamed ALLAM
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Patent number: 9785601Abstract: A device includes a first driver circuit coupled to a first bus line, where the first driver circuit includes a first delay element. The first delay element is configured to receive a first input signal and generate a first output signal. The first output signal transitions logic levels after a first delay period when the first input signal transitions from a logic high level to a logic low level. The first output signal transitions logic levels after a second delay period when the first input signal transitions from the logic low level to the logic high level. The first delay element includes a sense amplifier. The first driver circuit is configured to transmit the first output signal over the first bus line. The device also includes a second driver circuit configured to transmit a second output signal over a second bus line.Type: GrantFiled: February 17, 2016Date of Patent: October 10, 2017Assignee: QUALCOMM IncorporatedInventors: Baker S. Mohammad, Paul D. Bassett, Martin Saint-Laurent
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Patent number: 9673786Abstract: A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.Type: GrantFiled: April 12, 2013Date of Patent: June 6, 2017Assignee: QUALCOMM IncorporatedInventors: Seid Hadi Rasouli, Animesh Datta, Jay Madhukar Shah, Martin Saint-Laurent, Peeyush Kumar Parkar, Sachin Bapat, Ramaprasath Vilangudipitchai, Mohamed Hassan Abu-Rahma, Prayag Bhanubhai Patel
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Patent number: 9417643Abstract: A method includes receiving, at a voltage regulator, an activity adjustment signal from a digital circuit. The method also includes controlling one or more variable impedance elements of the voltage regulator to modify an output voltage provided to the digital circuit. The output voltage is based at least in part on the activity adjustment signal.Type: GrantFiled: March 15, 2013Date of Patent: August 16, 2016Assignee: Qualcomm IncorporatedInventors: Martin Saint-Laurent, Yuhe Wang
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Publication number: 20160162432Abstract: A device includes a first driver circuit coupled to a first bus line, where the first driver circuit includes a first delay element. The first delay element is configured to receive a first input signal and generate a first output signal. The first output signal transitions logic levels after a first delay period when the first input signal transitions from a logic high level to a logic low level. The first output signal transitions logic levels after a second delay period when the first input signal transitions from the logic low level to the logic high level. The first delay element includes a sense amplifier. The first driver circuit is configured to transmit the first output signal over the first bus line. The device also includes a second driver circuit configured to transmit a second output signal over a second bus line.Type: ApplicationFiled: February 17, 2016Publication date: June 9, 2016Inventors: Baker S. Mohammad, Paul D. Bassett, Martin Saint-Laurent
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Patent number: 9348402Abstract: A processor having a multi-Vt critical path is provided that includes both low-Vt devices and high-Vt devices. If the processor is operating in a high performance mode, the multi-Vt critical path is controlled so as to use the low-Vt devices. Conversely, if the processor is operating in a low power mode, the multi-Vt critical path is controlled so as to use the high-Vt devices. In this fashion, the complication of multiple processing cores is avoided in that a single processor core can operate in both the high performance mode and in the low power mode.Type: GrantFiled: February 19, 2013Date of Patent: May 24, 2016Assignee: QUALCOMM IncorporatedInventors: Joseph Victor Zanotelli, Martin Saint-Laurent
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Patent number: 9093995Abstract: A circuit includes a pulsed-latch circuit. The pulsed-latch circuit includes a first plurality of transistors. One or more of the first plurality of transistors is length-of-diffusion (LOD) protected.Type: GrantFiled: May 29, 2013Date of Patent: July 28, 2015Assignee: QUALCOMM IncorporatedInventors: Kashyap Ramachandra Bellur, HariKrishna Chintarlapalli Reddy, Martin Saint-Laurent, Pratyush Kamal, Prayag Bhanubhai Patel, Esin Terzioglu
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Patent number: 8995207Abstract: According to an embodiment, an apparatus includes a data storage device. Data to be stored in the data storage device is level shifted from a first voltage domain to a second voltage domain prior to being stored within the data storage device. The data storage device is powered by the second voltage domain. The apparatus further includes a circuit that is powered by the second voltage domain and that is responsive to data output by the data storage device.Type: GrantFiled: August 12, 2011Date of Patent: March 31, 2015Assignee: QUALCOMM IncorporatedInventors: Christopher Edward Koob, Jen Tsung Lin, Manojkumar Pyla, Martin Saint-Laurent
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Patent number: 8994458Abstract: A method includes determining a control setting and selectively stopping oscillation of an oscillator after a time period. The oscillator is configured to remain in an active mode after the time period. The method further includes applying the control setting to the oscillator.Type: GrantFiled: November 8, 2011Date of Patent: March 31, 2015Assignee: QUALCOMM IncorporatedInventor: Martin Saint-Laurent
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Publication number: 20140354338Abstract: A circuit includes a pulsed-latch circuit. The pulsed-latch circuit includes a first plurality of transistors. One or more of the first plurality of transistors is length-of-diffusion (LOD) protected.Type: ApplicationFiled: May 29, 2013Publication date: December 4, 2014Inventors: Kashyap Ramachandra Bellur, HariKrishna Chintarlapalli Reddy, Martin Saint-Laurent, Pratyush Kamal, Prayag Bhanubhai Patel, Esin Terzioglu
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Publication number: 20140306735Abstract: A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.Type: ApplicationFiled: April 12, 2013Publication date: October 16, 2014Applicant: QUALCOMM IncorporatedInventors: Seid Hadi Rasouli, Animesh Datta, Jay Madhukar Shah, Martin Saint-Laurent, Peeyush Kumar Parkar, Sachin Bapat, Ramaprasath Vilangudipitchai, Mohamed Hassan Abu-Rahma, Prayag Bhanubhai Patel