Abstract: The disclosure includes a latch structure and self-adjusting pulse generator using the latch. In an embodiment, the system includes a first latch and a pulse generator coupled to provide a timing signal to the first latch. The pulse generator includes a second latch that has characteristics matching the first latch.

Abstract: A method is disclosed that includes propagating data via a first data path of a sequential circuit element in response to a clock signal received at a single clocked transistor of the sequential circuit element. The method also includes retaining information related to the data propagated via the first path at a retention circuit element of a second data path, where the first data path includes a first transistor that is responsive to an output of the single clocked transistor. The first transistor has a higher current flow capacity than a second transistor associated with the second data path.

Abstract: In an embodiment, a method is disclosed that includes receiving a clock signal at a delay chain of a circuit device and determining a value of the clock signal at a selected point within the delay chain. The method also includes adjusting the selected point when the value does not indicate detection of an edge of the clock signal.

Abstract: In particular illustrative embodiments, circuit devices and methods of controlling a voltage swing are disclosed. The method includes receiving a signal at an input of a digital circuit device including a capacitive node. The method also includes selectively activating a voltage level adjustment element to regulate an electrical discharge path from the capacitive node to an electrical ground to prevent complete discharge of the capacitive node. In a particular illustrative embodiment, the received signal may be a clock signal.

Abstract: A clock distribution network for clock distribution in an integrated circuit (IC) using digital feedback for skew compensation and jitter filtering. In an embodiment, a number of clock processor nodes are distributed throughout the clock distribution network on the IC at respective local clock regions. A master clock generator generates a master clock for distribution to the clock processor nodes, via the clock distribution network, to compensate clock skew and filter clock jitter locally at the respective local clock regions.

Abstract: A logic device includes a data input, a scan test input, a clock demultiplexer, and a master latch. The clock demultiplexer is responsive to a clock input to selectively provide a first clock output and a second clock output. The master latch is coupled to the data input and to the scan test input and includes an output. The master latch is responsive to the first clock output of the clock demultiplexer and the second clock output of the clock demultiplexer to selectively couple the data input or the scan test input to the output.

Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Reduced glitch occurs in switching from a first clock input to a second clock input driving a clock multiplexer. The clock multiplexer receives a first clock input and provides a clock output and determines a low phase output level in the clock output in response to a low phase input level in the first clock output. For a limited period of time, a low phase output level is forced irrespective of the phase level of the first clock input signal. The clock multiplexer receives a second clock input and determines a low phase input level in the second clock input signal. Switching to providing the clock output in response to the second clock input occurs during the low phase input level in the second clock input signal. Then, the output of the clock multiplexer follows the phase level of the second clock signal.

Abstract: A clock distribution network for clock distribution in an integrated circuit (IC) using digital feedback for skew compensation and jitter filtering. In an embodiment, a number of clock processor nodes are distributed throughout the clock distribution network on the IC at respective local clock regions. A master clock generator generates a master clock for distribution to the clock processor nodes, via the clock distribution network, to compensate clock skew and filter clock jitter locally at the respective local clock regions.

Abstract: A clock distribution network for clock distribution in an integrated circuit (IC) using digital feedback for skew compensation and jitter filtering. In an embodiment, a number of clock processor nodes are distributed throughout the clock distribution network on the IC at respective local clock regions. A master clock generator generates a master clock for distribution to the clock processor nodes, via the clock distribution network, to compensate clock skew and filter clock jitter locally at the respective local clock regions.

Abstract: A clock distribution network for clock distribution in an integrated circuit (IC) using digital feedback for skew compensation and jitter filtering.

Abstract: A clock distribution network is provided which includes variable-delay element. The variable-delay element consists of an inverter and a digitally adjustable resistor. The digitally adjustable resistor includes a plurality of transistors provided in plurality of rows and a plurality of columns. The variable-delay element functions logically equivalent to the inverter in which the delay is varied in accordance with the variance in resistance of the digitally adjustable resistor.

Abstract: A clock distribution network is provided which includes variable-delay element. The variable-delay element consists of an inverter and a digitally adjustable resistor. The digitally adjustable resistor includes a plurality of transistors provided in plurality of rows and a plurality of columns.