Patents by Inventor Martin Schmatz
Martin Schmatz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090201973Abstract: An apparatus is provided for transmitting data signals and additional information signals having partially overlapping frequency bands simultaneously within a wire based communication system over the same wired medium using a spread spectrum technique for modulating the additional information signals.Type: ApplicationFiled: February 13, 2008Publication date: August 13, 2009Applicant: International Business Machines CorporationInventors: Hayden C. Cranford, JR, Martin Schmatz
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Patent number: 7447278Abstract: The apparatus for transmitting and receiving data according to the invention contains a transmitter (1) for serial data transmission and a receiver (3) for receiving a transmitted data signal (g(t)). The receiver (3) in turn comprises a first sample latch (11) for sampling the received data signal (g(t)) with a first clock (f2) and for generating a first sample value (an). The receiver (3) also comprises a second sample latch (13) for sampling a first shifted received data signal (g(t)+V1) with a second clock (f1) and for generating a second sample value (yn). The receiver (3) further comprises a third sample latch (14) for sampling a second shifted received data signal (g(t)?V1) with the second clock (f1) and for generating a third sample value (zn). Finally the receiver (3) comprises a logic unit (15) for recovering data (dn) out of said first, second and third sample values (an, yn, zn).Type: GrantFiled: May 20, 2004Date of Patent: November 4, 2008Assignee: International Business Machines CorporationInventors: Christian Menolfi, Martin Schmatz, Thomas Toifl
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Patent number: 7418069Abstract: The invention is directed to a clock data recovery system for resampling a clock signal according to an incoming data signal. The clock data recovery system comprises a clock generator for generating the clock signal and a phase adjustment unit for generating sampling phases dependent on a phase adjustment control signal. It also comprises a data sampling unit operable to generate a stream of input samples and an edge detector for generating therefrom an internal early signal and an internal late signal. A phase adjustment control unit is disposed for generating under use of the early signal and the late signal the phase adjustment control signal. The phase adjustment control unit is feedable with an external early/late signal and/or comprises an output for delivering an export early/late signal.Type: GrantFiled: December 28, 2007Date of Patent: August 26, 2008Assignee: International Business Machines CorporationInventors: Martin Schmatz, Hayden C. Cranford, Vernon R. Norman
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Publication number: 20080112521Abstract: The invention is directed to a clock data recovery system for resampling a clock signal according to an incoming data signal. The clock data recovery system comprises a clock generator for generating the clock signal and a phase adjustment unit for generating sampling phases dependent on a phase adjustment control signal. It also comprises a data sampling unit operable to generate a stream of input samples and an edge detector for generating therefrom an internal early signal and an internal late signal. A phase adjustment control unit is disposed for generating under use of the early signal and the late signal the phase adjustment control signal. The phase adjustment control unit is feedable with an external early/late signal and/or comprises an output for delivering an export early/late signal.Type: ApplicationFiled: December 28, 2007Publication date: May 15, 2008Inventors: Martin Schmatz, Hayden Cranford, Vernon Norman
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Patent number: 7346094Abstract: A system and method is provided for transmitting data signals and additional information signals having partially overlapping frequency bands simultaneously within a wire based communication system over the same wired medium using a spread spectrum technique for modulating the additional information signals.Type: GrantFiled: December 13, 2002Date of Patent: March 18, 2008Assignee: International Business Machines CorporationInventors: Hayden C. Cranford, Jr., Martin Schmatz
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Patent number: 7315594Abstract: The invention is directed to a clock data recovery system for resampling a clock signal to an incoming data signal. The clock data recovery system comprises a clock generator for generating the clock signal and a phase adjustment unit for generating sampling phases dependant on a phase adjustment control signal. It also comprises a data sampling unit operable to generate a stream of input samples and an edge detector for generating therefrom an internal early signal and an internal late signal. A phase adjustment control unit is disposed for generating under use of the early signal and the late signal the phase adjustment control signal. The phase adjustment control unit is feedable with an external early/late signal and/or comprises an output for delivering an export early/late signal.Type: GrantFiled: July 15, 2002Date of Patent: January 1, 2008Assignee: International Business Machines CorporationInventors: Martin Schmatz, Hayden C. Cranford, Vernon R. Norman
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Publication number: 20070286190Abstract: A transmitter-receiver crossbar for a packet switch comprising a transmitter having an array of transmitting ports, each having one or more transmitting antennas to transmit a radio signal and a receiver having an array of receiving ports, each having one or more receiving antennas to receive the radio signal.Type: ApplicationFiled: May 16, 2007Publication date: December 13, 2007Applicant: International Business Machines CorporationInventors: Wolfgang Denzel, Ronald Luijten, Thomas Morf, Martin Schmatz
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Publication number: 20070242741Abstract: Disclosed are a receiver circuit, method and design architecture of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER). An integrating receiver is combined with a decision feedback equalizer along with the appropriate (CDR) loop phase detector to maintain a single sample per bit requirement. The incoming voltage is converted to a current and connected to a current summing node. Weighted currents determined by the values of previously detected bits and their respective feedback coefficients are also connected to this node. Additionally, the summed currents is integrated and converted to a voltage. A sampler is utilized to make a bit decision based on the resulting voltage. After sampling, the integrator is reset before analysis of the next bit. The necessary amplification is achieved by maximizing the sensitivity of the latch, using integration in front of the data latch.Type: ApplicationFiled: April 18, 2006Publication date: October 18, 2007Inventors: Juan Carballo, Hayden Cranford, Gareth Nicholls, Vernon Norman, Martin Schmatz
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Publication number: 20070101086Abstract: A system, method and storage medium for deriving clocks in a memory system. The method includes receiving a reference oscillator clock at a hub device. The hub device is in communication with a controller channel via a controller interface and in communication with a memory device via a memory interface. A base clock operating at a base clock frequency is derived from the reference oscillator clock. A memory interface clock is derived by multiplying the base clock by a memory multiplier. A controller interface clock is derived by multiplying the base clock by a controller multiplier. The memory interface clock is applied to the memory interface and the controller interface clock is applied to the controller interface.Type: ApplicationFiled: October 31, 2005Publication date: May 3, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Frank Ferraiolo, Kevin Gower, Martin Schmatz
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Publication number: 20070075785Abstract: A phase locked loop (PLL) which includes a phase frequency detector coupled with a time to digital converter capable of comparing a reference signal with an oscillator signal and generating a digital value representing the phase difference between the reference signal and the oscillator signal. The PLL further includes a state machine for phase acquisition that is capable of generating a control value depending on the digital value, and a controllable oscillator that is capable of generating the oscillator signal depending on the control value.Type: ApplicationFiled: August 31, 2006Publication date: April 5, 2007Inventors: Marcel Kossel, Thomas Morf, Martin Schmatz, Silvan Wehrli
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Publication number: 20070061665Abstract: The forward error correction based clock and data recovery system according to the invention comprises a data latch (16) for intermediately storing received data, which is triggered by a sampling clock (sclk). The system further comprises an error determination unit (20, 21) for determining whether and which of the sampled received data is wrong, and for generating out of it a phase/frequency correction signal (ctrl). Furthermore, the system comprises a clock generator (23, 24, 25) for generating the sampling clock (sclk) depending on the correction signal (ctrl).Type: ApplicationFiled: August 29, 2005Publication date: March 15, 2007Applicant: International Business Machines CorporationInventors: Hayden Cranford, Martin Schmatz, Thomas Toifl
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Publication number: 20070033466Abstract: A receiver for a serial link port that is enhanced by a clock-data-recovery loop connected to the forwarded clock signal lane. The receiver includes a phase interpolation means controlled by a phase position logic which gets its update signal from local phase update signals of the clock-data-recovery loop via a digital low pass filter. The receiver also provides a global phase update source selection logic to control which clock-data-recovery loop is distributing phase update information, and which clock-data-recovery loop is receiving phase update information based on the clock analysis block.Type: ApplicationFiled: July 11, 2006Publication date: February 8, 2007Applicant: International Business Machines CorporationInventors: Peter Buchmann, Martin Schmatz
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Patent number: 7149269Abstract: A receiver for clock and data recovery includes n sampling latches (SL1 . . . SLn) for determining n sample values (SV1 . . . SVn) of a reference signal (Ref2) at n sampling phases (?1a . . . (?na) having sampling latch inputs and sampling latch outputs. The receiver further includes a phase position analyzer (5) connected to the sampling latch outputs for generating an adjusting signal (AS) for adjusting the sampling phase (?1a . . . ?na), if the sample value (SV1 . . . SVn) deviates from a set point and a phase interpolator (9) for generating sampling phases (?1u . . . ?nu). A sampling phase adjusting unit (6) connected with its inputs to the phase position analyzer (5) and the phase interpolator (9) and with its outputs to the sampling latches (SL1 . . . SLn) is provided for generating adjusted sampling phases (?1a . . . ?na) depending on the sampling phases (?1u . . . ?nu) and said adjusting signal (AS).Type: GrantFiled: February 27, 2003Date of Patent: December 12, 2006Assignee: International Business Machines CorporationInventors: Hayden C. Cranford, Jr., Vernon R. Norman, Martin Schmatz
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Patent number: 7136592Abstract: An optical detector for receiving an optical signal transmitting via an optical fiber cable, comprises an array of photo-sensors for location in the path of the optical signal. A controller a controller detects which of the photo-sensors receives the optical signal in use, and derives a received signal from an output of any said photo-sensor so detected.Type: GrantFiled: August 9, 2001Date of Patent: November 14, 2006Assignee: International Business Machines CorporationInventor: Martin Schmatz
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Patent number: 7050522Abstract: A phase rotator device for phase shifting an oscillating signal, including an input device having at least one input channel for receiving at least one phase of the oscillating signal and an output device having at least one output channel for delivering at least one phase of the oscillating signal with a controlled phase shift. For each output channel, the phase rotator includes a weighting device for weighting the value of the oscillating signal at each input channel by a respective weighting coefficient, and a summing device for summing the weighted signal values at each input channel and delivering the summed value as a shifted output phase at the output channel. Additionally, the phase rotator device includes a weighting coefficient supply device responsive to a phase shift control signal for controllably supplying evolving weighting coefficients to the weighting device, thereby to create a phase shift at the output channel.Type: GrantFiled: May 22, 2001Date of Patent: May 23, 2006Assignee: International Business Machines CorporationInventor: Martin Schmatz
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Publication number: 20060045224Abstract: Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data signal are disclosed. In particular, embodiments extend the CDR loop by slowing the clock rate with respect to the sampling clock. For instance, the slower clock rate may be implemented by dividing the frequency of the sampling clock by a number such as 128, slowing a sampling clock frequency designed to handle multiple gigabits per second (Gbps) to a frequency of less than one kilohertz (Khz). In addition to the reduced power consumption realized by operating at a lower frequency, the slower clock rate allows components of the CDR loop circuitry to operate a lower operating voltage reducing power consumption by the CDR loop even more.Type: ApplicationFiled: August 11, 2004Publication date: March 2, 2006Applicant: International Business Machines CorporationInventors: Hayden Cranford, Gareth Nicholls, Vernon Norman, Martin Schmatz, Karl Selander, Michael Sorna
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Publication number: 20060029177Abstract: A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL), a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.Type: ApplicationFiled: October 13, 2005Publication date: February 9, 2006Applicant: International Business Machines CorporationInventors: Hayden Cranford, Vernon Norman, Martin Schmatz
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Publication number: 20060008042Abstract: The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the transmitter portion and receiver portion comprising a phase locked loop (PLL) circuit. The PLL circuit comprises a voltage control oscillator, a frequency divider, a phase-frequency detector, a charge pump and a multi-pole loop filter. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop.Type: ApplicationFiled: September 13, 2005Publication date: January 12, 2006Applicant: International Business Machines CorporationInventors: Hayden Cranford, Stacy Garvin, Vernon Norman, Paul Owczarski, Martin Schmatz, Joseph Stevens
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Patent number: 6981168Abstract: A clock data recovery system is provided for resampling a clock signal according to an incoming data signal stream. It comprises a clock generator for generating said clock signal wherein one of the frequency and phase of that clock signal is dependent upon a control signal. It is further provided a phase detector operable to detect the phase difference between said clock signal and said incoming data signal stream and is operable to generate a phase difference signal. A loop controller has a variable-gain and is operable to control said clock generator by generating said control signal. That control signal is dependent in said phase difference signal and that variable-gain. The variable-gain is dependent upon a transition rate of the incoming data signal stream. The loop controller can comprise a low-pass filter to generate from the phase difference signal a low-pass filered phase signal and to adjust the bandwidth of the clock data recovery system.Type: GrantFiled: October 30, 2002Date of Patent: December 27, 2005Assignee: International Business Machines CorporationInventors: Martin Schmatz, Christian Menofli, Thomas Morf
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Publication number: 20050195863Abstract: Aspects of providing automatic adaptation to frequency offsets in high speed serial links are described. First signals for phase adjusts in a receiver link are adjusted by detecting trends in the first signals to generate second signals, the second signals improving a rate of compensation for the frequency offsets by the phase adjusts. An up/down counter is included for counting signals for phase adjustments by a clock-data-recovery loop of a serial receiver. An adder is coupled to the up/down counter and outputs accumulated data indicative of a trend in the phase adjustments. Combinatorial logic coupled to the adder adapts the signals based on the accumulated data.Type: ApplicationFiled: March 2, 2004Publication date: September 8, 2005Applicant: International Business Machines CorporationInventors: Hayden Cranford, Gareth Nicholls, Bobak Modaress-Razavi, Vernon Norman, Martin Schmatz