Abstract: The method for determining jitter of a signal in a serial link according to the invention comprising the following steps: First, a section of the signal transmitted via a transmission channel is sampled at different sampling times. The total number of edges in the section is determined. The neighboring sample values are analyzed and from that a statistical value is formed. From the statistical value and the total number of edges a figure of merit is determined. Finally, by means of a look-up table or a jitter-versus-figure of merit curve, the total jitter corresponding to the figure of merit is derived.

Abstract: The present invention provides integrated line drivers useable for driving data signals with high data rates wherein the area consumption of the line driver is minimized and wherein the influence of electrostatic discharge devices and process tolerances are minimized too. An example of an integrated line driver according to the invention comprises a first driver stage followed by a second driver stage, and a feedback unit forming with the second driver stage a control loop. The integrated line drivers are useable for driving data signals with high data rates wherein the area consumption of the line driver is minimized and wherein the influence of ESD devices and process tolerances are minimized. Advantageously, the integrated line driver according to the invention complies with chip design methodologies, where 10 or more routing metal layers are used.

Abstract: A method and system for testing a high-speed circuit is disclosed. The method and system include obtaining a high-speed statistical signature of the high-speed circuit using a conventional tester. The method and system further include comparing the high-speed statistical signature of the high-speed circuit to an expected signature. Consequently, it can be determined whether the high-speed circuit functions within the desired parameters.

Abstract: The apparatus for transmitting and receiving data according to the invention contains a transmitter (1) for serial data transmission and a receiver (3) for receiving a transmitted data signal (g(t)). The receiver (3) in turn comprises a first sample latch (11) for sampling the received data signal (g(t)) with a first clock (f2) and for generating a first sample value (an). The receiver (3) also comprises a second sample latch (13) for sampling a first shifted received data signal (g(t)+V1) with a second clock (f1) and for generating a second sample value (yn). The receiver (3) further comprises a third sample latch (14) for sampling a second shifted received data signal (g(t)?V1) with the second clock (f1) and for generating a third sample value (zn). Finally the receiver (3) comprises a logic unit (15) for recovering data (dn) out of said first, second and third sample values (an, yn, zn).

Abstract: Methods, systems and apparatus for adjusting parameters of a serial link is introduced. A bit pattern sequence that was transmitted via a transmission channel of the serial link is sampled at different sampling times. For the different sampling times, corresponding bit error rate values are determined. The bit error rate values result in a curve. Based on this curve, a quality value derived, that is used for adjusting parameters of an equalizer unit of the serial link.

Abstract: The invention is directed to a clock data recovery system for resampling a clock signal to an incoming data signal. The clock data recovery system comprises a clock generator for generating the clock signal and a phase adjustment unit for generating sampling phases dependant on a phase adjustment control signal. It also comprises a data sampling unit operable to generate a stream of input samples and an edge detector for generating therefrom an internal early signal and an internal late signal. A phase adjustment control unit is disposed for generating under use of the early signal and the late signal the phase adjustment control signal. The phase adjustment control unit is feedable with an external early/late signal and/or comprises an output for delivering an export early/late signal.

Abstract: The receiver for clock and data recovery according to the invention comprises n sampling latches (SL1 . . . SLn) for determining n sample values (SV1 . . . SVn) of a reference signal (Ref2) at n sampling phases (&phgr;1a . . . (&phgr;na) having sampling latch inputs and sampling latch outputs. The receiver further comprises a phase position analyzer (5) connected to said sampling latch outputs for generating an adjusting signal (AS) for adjusting the sampling phase (&phgr;1a . . . (&phgr;na), if the sample value (SV1 . . . SVn) deviates from a set point and a phase interpolator (9) for generating sampling phases (&phgr;1u . . . (&phgr;nu). A sampling phase adjusting unit (6) connected with its inputs to the phase position analyzer (5) and the phase interpolator (9) and with its outputs to the sampling latches (SL1 . . . SLn) is provided for generating adjusted sampling phases (&phgr;1a . . . (&phgr;na) depending on said sampling phases (&phgr;1u . . . (&phgr;nu) and said adjusting signal (AS).

Abstract: A system and method is provided for transmitting data signals and additional information signals having partially overlapping frequency bands simultaneously within a wire based communication system over the same wired medium using a spread spectrum technique for modulating the additional information signals.

Abstract: A clock data recovery system is provided for resampling a clock signal according to an incoming data signal stream. It comprises a clock generator for generating said clock signal wherein one of the frequency and phase of that clock signal is dependent upon a control signal. It is further provided a phase detector operable to detect the phase difference between said clock signal and said incoming data signal stream and is operable to generate a phase difference signal. A loop controller has a variable-gain and is operable to control said clock generator by generating said control signal. That control signal is dependent in said phase difference signal and that variable-gain. The variable-gain is dependent upon a transition rate of the incoming data signal stream. The loop controller can comprise a low-pass filter to generate from the phase difference signal a low-pass filered phase signal and to adjust the bandwidth of the clock data recovery system.

Abstract: An optical connector includes a plug unit and a counter plug unit, each comprise of two components. Each component comprises a receiving portion for receiving and fixing at least two optical fibers and an adjusting portion having adjusters to adjust the optical fibers in a defined position. The adjusting portion provides for the insertion of a connector by having elongate V-shaped grooves, with one of the optical fibers being aligned in each of the grooves by the adjusting portion.

Abstract: An optical detector for receiving an optical signal transmitting via an optical fiber cable, comprises an array of photo-sensors for location in the path of the optical signal. A controller a controller detects which of the photo-sensors receives the optical signal in use, and derives a received signal from an output of any said photo-sensor so detected.

Abstract: A phase rotator device for phaaase shifting an oscillating sign, including an input device having at least one input channel for receiving at least one phase of the oscillating signal and an output device having at least one output channel for delivering at least one phase of the oscillating signal with a controlled phase shift. For each output channel, the phase rotator includes a weighting device for weighting the value of the oscillating signal at each input channel by a respective weighting coefficient, and a summing device for summing the weighted signal values at each input channel and delivering the summed value as a shifted output phase at the output channel. Additionally, the phase rotator device includes a weighting coefficient supply device responsive to a phase shift control signal for controllably supplying evolving weighting coefficients to the weighting device, thereby to create a phase shift at the output channel.

Abstract: An optical connector includes a plug unit and a counter plug unit, each comprise of two components. Each component comprises a receiving portion for receiving and fixing at least two optical fibers and an adjusting portion having adjusters to adjust the optical fibers in a defined position. The adjusting portion provides for the insertion of a connector by having elongate V-shaped grooves, with one of the optical fibers being aligned in each of the grooves by the adjusting portion.