Abstract: An imaging device includes an imager to capture an image, a controller to control the imager to define a dynamic electronic fovea. The dynamic electronic fovea is defined by a subset of pixels of the imager. The subset of pixels for the fovea is driven differently from a remainder of pixels of the imager.

Abstract: A solid state drive includes DRAM logical flash and flash memory, in which system processor reads and writes only to the DRAM logical flash which minimizes writes to the flash memory. A method for operation of a solid state flash device includes writing, by a CPU, to a solid state drive by sending commands and data to DRAM logical flash using flash commands and formatting.

Abstract: A receiver of an optical communications system includes a set of two or more analog-to digital A/D converters, a respective transform block connected to an output of each A/D converter, and a summation block. Each A/D converter samples a respective low-bandwidth analog signal comprising a respective portion of a high-bandwidth data signal. Each transform block calculates a set of spectral components of the respective low-bandwidth analog signal. The summation block combines respective spectral components calculated by each transform block to construct spectral terms of a combined signal having a spectrum corresponding to that of the high-bandwidth data signal.

Abstract: A system and method to achieve low power and/or low supply operation of a delta-sigma modulator by taking advantage of the inherent virtual ground of the delta-sigma loop to make the input to a low power integrator small and largely independent of the input signal. This results in improved linearity of the integrator and relaxed constraints on the supply for the first stage integrator. The architecture also enables direct access to the quantization error of the feedback loop and thus can be used to either/or: 1. Calibrate the modulator, 2. Achieve reduced quantization noise, 3. Stabilize the loop by compensating for excess loop delay. Low voltage common-mode-feedback is also achieved using the techniques described.

Abstract: A system and method for processing a signal with a filter employing FIR and/or IIR elements. The required controller function is decomposed into primary FIR and/or IIR elements and a compensation filter is provided to address the latency in the primary elements, which would result in undesired operation of the filter. Several configurations of suitable filters are discussed, including multi-rate filters and filters with reduced power requirements.

Abstract: A multi-touch sensing system and a method for estimating a location of at least one touch point are provided. The multi-touch sensing system includes a panel, a grid of conductor disposed on the panel, a driver array connected to the grid, a receiver array connected to the grid, a signal processing system, and a controller. The method involves transmitting drive signals to the grid, receiving signals from the grid, estimating a capacitance, and transforming the capacitance into touch coordinates.

Abstract: In capacitive touch panels arrays, self and mutual capacitances of embedded wires in rows and columns are measured to estimate the position of fingers, styli and the like. For precise measurement of position and for sensitivity to small objects it is desirable to have these wires closely spaced; but this causes the number of connections to the panel to become large and problematic. Sensing lines may share connections by permuting their order, thus reducing the number of pins required on a touch-panel controller chip; in cabling between a touch panel and its controller; and in memory requirements for a touch-panel controller.

Abstract: In capacitive touch panels arrays, self- and mutual capacitances of embedded sense lines in rows and columns are measured to estimate the position of probes such as fingers, styli and the like. Signals are driven onto the sense lines in order to estimate capacitances, but it is desired to keep these signals as weak as possible in order to minimize power consumption, voltage drive requirements and electromagnetic interference. Accurate detection of the position of the probe, particularly with weak signals, is rendered difficult by its motion. Techniques are proposed for power-efficient drive signals and related techniques proposed that are operable to estimate velocity. Dual receive structures with similar properties are proposed.

Abstract: A system and method to achieve low power and/or low supply operation of a delta-sigma modulator by taking advantage of the inherent virtual ground of the delta-sigma loop to make the input to a low power integrator small and largely independent of the input signal. This results in improved linearity of the integrator and relaxed constraints on the supply for the first stage integrator. The architecture also enables direct access to the quantization error of the feedback loop and thus can be used to either/or: 1. Calibrate the modulator, 2. Achieve reduced quantization noise, 3. Stabilize the loop by compensating for excess loop delay. Low voltage common-mode-feedback is also achieved using the techniques described.

Abstract: An analog to digital conversion system is disclosed which converts an analog signal to a digital representation thereof at a first sampling rate by distributing the analog signal to at least two signal paths, at least one signal path including a limiting mixer to mix the signal with a respective selected square wave and a smoothing (low pass) filter to filter the mixed signal before providing the mixed and filtered signal to a subconverter, the subconverter having a sampling rate less than the first sampling rate, and a digital matrix filter to combine the digital output of each subconverter to form a digital representation of the analog signal as sampled at the first rate.

Abstract: A solid state drive includes DRAM logical flash and flash memory, in which system processor reads and writes only to the DRAM logical flash which minimizes writes to the flash memory. A method for operation of a solid state flash device includes writing, by a CPU, to a solid state drive by sending commands and data to DRAM logical flash using flash commands and formatting.

Abstract: An analog to digital conversion system is disclosed which converts an analog signal to a digital representation thereof at a first sampling rate by distributing the analog signal to at least two signal paths, at least one signal path including a limiting mixer to mix the signal with a respective selected square wave and a smoothing (low pass) filter to filter the mixed signal before providing the mixed and filtered signal to a subconverter, the subconverter having a sampling rate less than the first sampling rate, and a digital matrix filter to combine the digital output of each subconverter to form a digital representation of the analog signal as sampled at the first rate.

Abstract: A system and method of reducing the effects of nonidealities of ADCs in multipath converters is disclosed. The system and method employs a variety of measure and correction blocks to determine statistical properties of the output stream of the multipath converter and to apply corrections to the operation of the subconverters of the multipath converter based upon differences in the measured statistics and expected target values, either explicit or implicit, for those statistics. A variety of examples of possible measure and configuration blocks are disclosed, as is the cascading of the measure and correction blocks to correct multiple errors in the output of the multipath converter. Feedforward (purely digital) and feedback (analog and digital) solutions are both disclosed.

Abstract: A frequency decimation block for processing an analog input signal including a high-bandwidth data signal to generate a parallel set of parallel output signals, in which each output signal represents a respective portion of the high-bandwidth data signal. A preamplifier is provided for amplifying the input signal. A frequency domain divider divides the amplified input signal to generate a set of frequency band signals including a low frequency band signal, a mid-frequency band signal, and a high frequency band signal. Each frequency band signal is supplied to at least one signal path. A respective non-linear processor is connected in each of M signal paths processes the input signal using a respective branch signal to yield a corresponding composite signal. A respective Low-Pass Filter (LPF) is connected in each signal path, for low-pass filtering at least the composite signals to generate corresponding ones of the parallel output signals.

Abstract: An analog to digital conversion system is disclosed which converts an analog signal to a digital representation thereof at a first sampling rate by distributing the analog signal to at least two signal paths, at least one signal path including a limiting mixer to mix the signal with a respective selected square wave and a smoothing (low pass) filter to filter the mixed signal before providing the mixed and filtered signal to a subconverter, the subconverter having a sampling rate less than the first sampling rate, and a digital matrix filter to combine the digital output of each subconverter to form a digital representation of the analog signal as sampled at the first rate.

Abstract: A system and method for processing a signal with a filter employing FIR and/or IIR elements. The required controller function is decomposed into primary FIR and/or IIR elements and a compensation filter is provided to address the latency in the primary elements, which would result in undesired operation of the filter. Several configurations of suitable filters are discussed, including multi-rate filters and filters with reduced power requirements.

Abstract: A system and method for processing a signal with a filter employing FIR and/or IIR elements. The required controller function is decomposed into primary FIR and/or IIR elements and a compensation filter is provided to address the latency in the primary elements, which would result in undesired operation of the filter. Several configurations of suitable filters are discussed, including multi-rate filters and filters with reduced power requirements.

Abstract: A novel pulse density modulator is disclosed which includes at least one sigma delta modulator operating at a clock rate selected to provide a pre-selected timing resolution for sampling an input signal. The sigma delta modulator employs a hysteresis element to reduce the average transition rate of the output signal of the sigma delta modulator to reduce switching losses. The novel pulse density modulator can provide at least a two or three level output, as desired.

Abstract: An analog to digital conversion system is disclosed which converts an analog signal to a digital representation thereof at a first sampling rate by distributing the analog signal to at least two signal paths, at least one signal path including a limiting mixer to mix the signal with a respective selected square wave and a smoothing (low pass) filter to filter the mixed signal before providing the mixed and filtered signal to a subconverter, the subconverter having a sampling rate less than the first sampling rate, and a digital matrix filter to combine the digital output of each subconverter to form a digital representation of the analog signal as sampled at the first rate.

Abstract: A system and method of reducing the effects of nonidealities of ADCs in multipath converters is disclosed. The system and method employs a variety of measure and correction blocks to determine statistical properties of the output stream of the multipath converter and to apply corrections to the operation of the subconverters of the multipath converter based upon differences in the measured statistics and expected target values, either explicit or implicit, for those statistics. A variety of examples of possible measure and configuration blocks are disclosed, as is the cascading of the measure and correction blocks to correct multiple errors in the output of the multipath converter. Feedforward (purely digital) and feedback (analog and digital) solutions are both disclosed.