Abstract: An interprocessor communication system is used in a multiprocessor where each processor is simultaneously a transmitter and a receiver of data. A data bus having only two states, a default state and an active state (e.g. high and low levels), is coupled to a plurality of bi-directional bus transceivers. Each transceiver is coupled between a processor element and a data bus and has an enable input. When the transceiver is enabled, it propagates an active level received at one end, either the processor element end or the data bus end, to the other end. The active state dominates on the interprocessor bus, so for instance, when multiple processors transmit, if any processor transmits a low level, then the bus will be low and all processors with enabled transceivers will also receive that low signal. This can be used for broadcasting data or combine operations such as AND or minimum.

Abstract: Methods of holding auctions over the Internet and telephone systems are known in the art but generally share the following problems: it is difficult for the auctioneer to identify bidders; telephone conferences are very noisy when they have a large number of participants; there is no method of ejecting a bidder who chooses to interfere with the auction; and it is difficult to enforce payment because it is difficult to verify the identity and creditworthiness of bidders. The invention provides for an auction system where bidders are identified using authentication or similar techniques, and their bids are filtered to reduce noise and eliminate unwanted bids or comments before being broadcast to the balance of the bidders. Other optional features are also described such as the recording and timestamping of bids.

Abstract: A complex filter minimizing mismatch error by averaging the mismatch error by integrating the real and imaginary input signals using the same integrator. A further advantage is that, as compared to known devices, the complex filter uses fewer number of components thereby reducing the consumed power. The complex filter may be used in a complex bandpass sigma-delta modulator, thereby increasing the performance of the sigma-delta modulator. The complex filter used in a sigma-delta modulator analog to digital converter increases performance of the analog to digital conversion since the mismatch noise is minimized. The complex bandpass sigma-delta modulator analog to digital converter include any number of complex filter stages.

Abstract: A digital computer performs read-modify-write (RMW) processing on each bit of a row of memory in parallel, in one operation cycle, comprising: (a) addressing a memory, (b) reading each bit of a row of data from the memory in parallel, (c) performing the same computational operation on each bit of the data in parallel, using an arithmetic logic unit (ALU) in a dedicated processing element, and (d) writing the result of the operation back into the original memory location for each bit in the row.

Abstract: A random access memory chip comprising static random access storage elements, word lines and bit lines connected to the storage elements, a sense amplifier connected to each of the bit lines, a separate processor element connected to each of the sense amplifiers, apparatus for addressing a word line, and apparatus for applying a single instruction to the processor elements, whereby the instructed processor elements are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the addressed word line. A method of operating a digital computer comprising in one operation cycle, addressing a memory, reading each of a row of data from the memory in parallel, and performing an operation function on each bit of the data in parallel to provide a result.

Abstract: A random access memory chip is comprised of static random access storage elements, word lines, and bit lines connected to the storage elements, a sense amplifier connected to each of the bit lines, a separate processor element connected to each of the sense amplifiers, apparatus for addressing a word line, and apparatus for applying a single instruction to the processor elements, whereby the instructed processor elements are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the addressed word line. A method of operating a digital computer is comprised of in one operation cycle, addressing a memory, reading each of a row of data from the memory in parallel, and performing a same operation function on each bit of the data in parallel to provide a result.