Patents by Inventor Martin Taillefer

Martin Taillefer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140195741
    Abstract: Type casting in a managed code system is described. The managed code system includes managed memory as well as shared memory located outside of the managed memory. The managed memory has multiple managed memory portions, each corresponding to a computing entity, such as a processes. The type system permits obtaining of data from shared memory using type casting to thereby assign the data a type that supports type casting. The type is a valid type casting type that satisfies certain requirements that allow the type to be assigned while maintaining type safety.
    Type: Application
    Filed: January 4, 2013
    Publication date: July 10, 2014
    Applicant: Microsoft Corporation
    Inventor: Martin Taillefer
  • Publication number: 20140195862
    Abstract: Handing errors in program execution. The method includes identifying a set including a plurality of explicitly identified failure conditions. The method further includes determining that one or more of the explicitly identified failure conditions has occurred. As a result, the method further includes halting a predetermined first execution scope of computing, and notifying another scope of computing of the failure condition. An alternative embodiment may be practiced in a computing environment, and includes a method handing errors. The method includes identifying a set including a plurality of explicitly identified failure conditions. The method further includes determining that an error condition has occurred that is not in the set including a plurality of explicitly identified failure conditions. As a result, the method further includes halting a predetermined first execution scope of computing, and notifying another scope of computing of the failure condition.
    Type: Application
    Filed: January 4, 2013
    Publication date: July 10, 2014
    Applicant: MICROSOFT CORPORATION
    Inventors: Martin Taillefer, Jinsong Yu, John J. Duffy, Sean E. Trowbridge, Alexander D. Bromfield
  • Publication number: 20140195632
    Abstract: The environment and use of an immutable buffer. A computing entity acquires data or generates data and populates the data into the buffer, after which the buffer is classified as immutable. The classification protects the data populated within the immutable buffer from changing during the lifetime of the immutable buffer, and also protects the immutable buffer from having its physical address changed during the lifetime of the immutable buffer. As different computing entities consume data from the immutable buffer, they do so through views provided by a view providing entity. The immutable buffer architecture may also be used for streaming data in which each component of the streaming data uses an immutable buffer. Accordingly, different computing entities may view the immutable data differently without having to actually copy the data.
    Type: Application
    Filed: January 4, 2013
    Publication date: July 10, 2014
    Applicant: MICROSOFT CORPORATION
    Inventors: Jason Todd Hunter, Jinsong Yu, Martin Taillefer, Gregory Michael Neverov, Dmitry Kakurin, Ahmed Hassan Mohamed, John J. Duffy, Christopher Wellington Brumme, F. Soner Terek
  • Publication number: 20140196059
    Abstract: Enforcing limitations on hardware drivers. The method includes from a system kernel, assigning I/O resources to the system's root bus. From the root bus, the method further includes assigning a subset of the I/O resources to a device bus. Assigning a subset of the I/O resources to a device bus includes limiting the device bus to only be able to assign I/O resources that are assigned to it by the root bus. From the device bus, the method includes assigning I/O resources to a device through a device interface.
    Type: Application
    Filed: January 4, 2013
    Publication date: July 10, 2014
    Applicant: Microsoft Corporation
    Inventors: Yaron Weinsberg, Jinsong Yu, John Richardson, Christopher Wellington Brumme, Martin Taillefer
  • Patent number: 8776041
    Abstract: Mechanisms are disclosed for updating a virtual machine monitor (“VMM”). Facilities of a guest operating system running in a guest virtual machine managed by the VMM are leveraged to facilitate receiving an update package. The update package may contain updates for guest operating systems extensions in addition to a VMM update. An updater process, running in a guest operating system, extracts the VMM update and transfers it down to the VMM. Upon successful transfer, the updater process applies any necessary updates to guest operating systems extensions and then signals the VMM to commit the transferred VMM update.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: July 8, 2014
    Assignee: Microsoft Corporation
    Inventors: Naveen K. Kachroo, Martin Taillefer, Lonny Dean McMichael
  • Patent number: 8688951
    Abstract: Operating system virtual memory management for hardware transactional memory. A system includes an operating system deciding to unmap a first virtual page. As a result, the operating system removes the mapping of the first virtual page to the first physical page from the virtual memory page table. As a result, the operating system performs an action to discard transactional memory hardware state for at least the first physical page. Embodiments may further suspend hardware transactions in kernel mode. Embodiments may further perform soft page fault handling without aborting a hardware transaction, resuming the hardware transaction upon return to user mode, and even successfully committing the hardware transaction.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: April 1, 2014
    Assignee: Microsoft Corporation
    Inventors: Koichi Yamada, Gad Sheaffer, Ali-Reza Adl-Tabatabai, Landy Wang, Martin Taillefer, Arun Kishan, David Callahan, Jan Gray, Vadim Bassin
  • Patent number: 8650551
    Abstract: Various technologies and techniques are disclosed for providing a debugger for programs running under a transactional memory system. When running a particular program using the debugger, the system detects when a conflict occurs on at least one conflictpoint that was set in the particular program. A graphical user interface is provided that displays information related to the detected conflict. The graphical user interface can display transactional state and/or other details independently of a conflict. A conflictpoint can be assigned to one or more regions of source code in one or more transactions in the particular program. A conflictpoint can also be assigned to a particular variable in the particular program. When running the particular program in a debug mode, execution is stopped if a conflict occurs on any of the conflictpoints.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: February 11, 2014
    Assignee: Microsoft Corporation
    Inventor: Martin Taillefer
  • Publication number: 20130238579
    Abstract: Handling garbage collection and exceptions in hardware assisted transactions. Embodiments are practiced in a computing environment including a hardware assisted transaction system. A method includes beginning a hardware assisted transaction, raising an exception while in the hardware assisted transaction, including creating an exception object, determining that the transaction should be rolled back, and as a result of determining that the transaction should be rolled back, marshaling the exception object out of the hardware assisted transaction.
    Type: Application
    Filed: March 18, 2013
    Publication date: September 12, 2013
    Applicant: Microsoft Corporation
    Inventors: Jan Gray, Martin Taillefer, Yosseff Levanoni, Ali-Reza Adl-Tabatabai, Dave Detlefs, Vinod K. Grover, Michael Magruder, Gad Sheaffer
  • Patent number: 8521995
    Abstract: A method includes receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: August 27, 2013
    Assignee: Intel Corporation
    Inventors: Koichi Yamada, Gad Sheaffer, Jan Gray, Landy Wang, Martin Taillefer, Arun Kishan, Ali-Reza Adl-Tabatabai, David Callahan
  • Patent number: 8495329
    Abstract: An object reference is tagged with an isolation permission modifier. At least two permissions can be included, and in an example three permissions are included. In implementing the permissions, type modifiers for controlling access to type members through references pointing at an object are defined. One of the type modifiers is associated with each occurrence of a type name. Each of the of type modifiers defines a different access permission to restrict operations on the object to which the reference points.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: July 23, 2013
    Assignee: Microsoft Corporation
    Inventors: John J. Duffy, Steven Edward Lucco, Anders Hejlsberg, Martin Taillefer
  • Patent number: 8489864
    Abstract: Performing non-transactional escape actions within a hardware based transactional memory system. A method includes at a hardware thread on a processor beginning a hardware based transaction for the thread. Without committing or aborting the transaction, the method further includes suspending the hardware based transaction and performing one or more operations for the thread, non-transactionally and not affected by: transaction monitoring and buffering for the transaction, an abort for the transaction, or a commit for the transaction. After performing one or more operations for the thread, non-transactionally, the method further includes resuming the transaction and performing additional operations transactionally. After performing the additional operations, the method further includes either committing or aborting the transaction.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: July 16, 2013
    Assignee: Microsoft Corporation
    Inventors: Gad Sheaffer, Jan Gray, Martin Taillefer, Ali-Reza Adl-Tabatabai, Bratin Saha, Vadim Bassin, Robert Y. Geva, David Callahan
  • Patent number: 8484175
    Abstract: Various technologies and techniques are described for providing a transaction grouping feature for use in programs operating under a transactional memory system. The transaction grouping feature is operable to allow transaction groups to be created that contain related transactions. The transaction groups are used to enhance performance and/or operation of the programs. Different locking and versioning mechanisms can be used with different transaction groups. When running transactions, a hardware transactional memory execution mechanism can be used for one transaction group while a software transactional memory execution mechanism used for another transaction group.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: July 9, 2013
    Assignee: Microsoft Corporation
    Inventor: Martin Taillefer
  • Patent number: 8473921
    Abstract: Debugging software in systems with architecturally significant processor caches. A method may be practiced in a computing environment. The method includes acts for debugging a software application, wherein the software application is configured to use one or more architecturally significant processor caches coupled to a processor. The method includes beginning execution of the software application. A debugger is run while executing the software application. The software application causes at least one of reads or writes to be made to the cache in an architecturally significant fashion. The reads or writes made to the cache in an architecturally significant fashion are preserved while performing debugging operations that would ordinarily disturb the reads or writes made to the cache in an architecturally significant fashion.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: June 25, 2013
    Assignee: Microsoft Corporation
    Inventors: Martin Taillefer, Ali-Reza Adl-Tabatabai, Gad Sheaffer, Peter Lachner, Richard Wurdack, Darek Mihocka, Jan Gray
  • Patent number: 8402218
    Abstract: Handling garbage collection and exceptions in hardware assisted transactions. Embodiments are practiced in a computing environment including a hardware assisted transaction system. Embodiments includes acts for writing to a card table outside of a transaction; handling garbage collection compaction occurring when a hardware transaction is active by using a common global variable and instructing one or more agents to write to the common global variable any time an operation is performed which may change an object's virtual address; acts for managing a thread-local allocation context; acts for handling exceptions while in a hardware assisted transaction.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: March 19, 2013
    Assignee: Microsoft Corporation
    Inventors: Jan Gray, Martin Taillefer, Yosseff Levanoni, Ali-Reza Adl-Tabatabai, Dave Detlefs, Vinod K. Grover, Michael Magruder, Gad Sheaffer
  • Patent number: 8392929
    Abstract: One embodiment includes method acts for detecting race conditions. The method includes beginning a critical section, during which conflicting reads and writes should be detected to determine if a race condition has occurred. This is performed by executing at a thread one or more software instructions to place a software lock on data. As a result of executing one or more software instructions to place a software lock on data, several additional acts are performed. In particular, the thread places a software lock on the data locking the data for at least one of exclusive writes or reads by the thread. And, at a local cache memory local to the thread, the thread enters the thread's memory isolation mode enabling local hardware buffering of memory writes and monitoring of conflicting writes or reads to or from the cache memory to detect reads or writes by non-lock respecting agents.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: March 5, 2013
    Assignee: Microsoft Corporation
    Inventors: Martin Taillefer, Gad Sheaffer
  • Patent number: 8365016
    Abstract: In one embodiment, the present invention includes a method for selecting a first transaction execution mode to begin a first transaction in a unbounded transactional memory (UTM) system having a plurality of transaction execution modes. These transaction execution modes include hardware modes to execute within a cache memory of a processor, a hardware assisted mode to execute using transactional hardware of the processor and a software buffer, and a software transactional memory (STM) mode to execute without the transactional hardware. The first transaction execution mode can be selected to be a highest performant of the hardware modes if no pending transaction is executing in the STM mode, otherwise a lower performant mode can be selected. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: January 29, 2013
    Assignee: Intel Corporation
    Inventors: Jan Gray, Martin Taillefer, Yossi Levanoni, Ali-Reza Adl-Tabatabai, Dave Detlefs, Vinod Grover, Mike Magruder, Matt Tolton, Bratin Saha, Gad Sheaffer, Vadim Bassin
  • Patent number: 8356166
    Abstract: Minimizing code duplication in an unbounded transactional memory system. A computing apparatus including one or more processors in which it is possible to use a set of common mode-agnostic TM barrier sequences that runs on legacy ISA and extended ISA processors, and that employs hardware filter indicators (when available) to filter redundant applications of TM barriers, and that enables a compiled binary representation of the subject code to run correctly in any of the currently implemented set of transactional memory execution modes, including running the code outside of a transaction, and that enables the same compiled binary to continue to work with future TM implementations which may introduce as yet unknown future TM execution modes.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: January 15, 2013
    Assignee: Microsoft Corporation
    Inventors: Ali-Reza Adl-Tabatabai, Bratin Saha, Gad Sheaffer, Vadim Bassin, Robert Y. Geva, Martin Taillefer, Darek Mihocka, Burton Jordan Smith, Jan Gray
  • Publication number: 20120284485
    Abstract: Operating system virtual memory management for hardware transactional memory. A system includes an operating system deciding to unmap a first virtual page. As a result, the operating system removes the mapping of the first virtual page to the first physical page from the virtual memory page table. As a result, the operating system performs an action to discard transactional memory hardware state for at least the first physical page. Embodiments may further suspend hardware transactions in kernel mode. Embodiments may further perform soft page fault handling without aborting a hardware transaction, resuming the hardware transaction upon return to user mode, and even successfully committing the hardware transaction.
    Type: Application
    Filed: July 20, 2012
    Publication date: November 8, 2012
    Applicant: MICROSOFT CORPORATION
    Inventors: Koichi Yamada, Gad Sheaffer, Ali-Reza Adl-Tabatabai, Landy Wang, Martin Taillefer, Arun Kishan, David Callahan, Jan Gray, Vadim Bassin
  • Patent number: 8266387
    Abstract: Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. One or more central processing units are provided with transactional memory hardware that is operable to accelerate virtualization. The transactional memory hardware has a facility to maintain private state, a facility to render memory accesses from other central processing units visible to software, and support for atomic commit of the private state. The transactional memory hardware can be used, for example, to facilitate emulation of precise exception semantics. The private state is operable to enable an emulated state to remain inconsistent with an architectural state and only synchronized on certain boundaries. An optimized sequence of instructions is executed using chunk-accurate simulation to try and achieve a same end effect.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: September 11, 2012
    Assignee: Microsoft Corporation
    Inventors: Martin Taillefer, Darek Mihocka, Bruno Silva
  • Patent number: 8250331
    Abstract: Operating system virtual memory management for hardware transactional memory. A method may be performed in a computing environment where an application running on a first hardware thread has been in a hardware transaction, with transactional memory hardware state in cache entries correlated by memory hardware when data is read from or written to data cache entries. The data cache entries are correlated to physical addresses in a first physical page mapped from a first virtual page in a virtual memory page table. The method includes an operating system deciding to unmap the first virtual page. As a result, the operating system removes the mapping of the first virtual page to the first physical page from the virtual memory page table. As a result, the operating system performs an action to discard transactional memory hardware state for at least the first physical page. Embodiments may further suspend hardware transactions in kernel mode.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: August 21, 2012
    Assignee: Microsoft Corporation
    Inventors: Koichi Yamada, Gad Sheaffer, Ali-Reza Adl-Tabatabai, Landy Wang, Martin Taillefer, Arun Kishan, David Callahan, Jan Gray, Vadim Bassin