Abstract: A number of switching transitions of flip-flops during testing is kept below a threshold. Scan-in test data is applied to the flip-flops. Testing result data scanned-out from the flip-flops is captured, and a prediction is made of a number of switching transitions of the flip-flops between a current capture clock cycle and a next capture clock cycle—in particular, for the next capture clock cycle—thereby using the scan-in test data for the next capture clock cycle and the testing result data scanned-out of the current capture clock cycle. Furthermore, the testing setup values are modified before the next testing cycle is executed based on the prediction in order to enter a new configuration of a testing circuit such that the predicted number of switching transitions of the flip-flops stays below the threshold. The testing setup values comprise parameters for modifying the capture clock cycle and a seed value for generating test patterns.

Abstract: A number of switching transitions of flip-flops during testing is kept below a threshold. Scan-in test data is applied to the flip-flops. Testing result data scanned-out from the flip-flops is captured, and a prediction is made of a number of switching transitions of the flip-flops between a current capture clock cycle and a next capture clock cycle—in particular, for the next capture clock cycle—thereby using the scan-in test data for the next capture clock cycle and the testing result data scanned-out of the current capture clock cycle. Furthermore, the testing setup values are modified before the next testing cycle is executed based on the prediction in order to enter a new configuration of a testing circuit such that the predicted number of switching transitions of the flip-flops stays below the threshold. The testing setup values comprise parameters for modifying the capture clock cycle and a seed value for generating test patterns.

Abstract: A number of switching transitions of flip-flops during testing is kept below a threshold. Scan-in test data is applied to the flip-flops. Testing result data scanned-out from the flip-flops is captured, and a prediction is made of a number of switching transitions of the flip-flops between a current capture clock cycle and a next capture clock cycle—in particular, for the next capture clock cycle—thereby using the scan-in test data for the next capture clock cycle and the testing result data scanned-out of the current capture clock cycle. Furthermore, the testing setup values are modified before the next testing cycle is executed based on the prediction in order to enter a new configuration of a testing circuit such that the predicted number of switching transitions of the flip-flops stays below the threshold. The testing setup values comprise parameters for modifying the capture clock cycle and a seed value for generating test patterns.

Abstract: A number of switching transitions of flip-flops during testing is kept below a threshold. Scan-in test data is applied to the flip-flops. Testing result data scanned-out from the flip-flops is captured, and a prediction is made of a number of switching transitions of the flip-flops between a current capture clock cycle and a next capture clock cycle—in particular, for the next capture clock cycle—thereby using the scan-in test data for the next capture clock cycle and the testing result data scanned-out of the current capture clock cycle. Furthermore, the testing setup values are modified before the next testing cycle is executed based on the prediction in order to enter a new configuration of a testing circuit such that the predicted number of switching transitions of the flip-flops stays below the threshold. The testing setup values comprise parameters for modifying the capture clock cycle and a seed value for generating test patterns.

Abstract: Technical solutions are described for optimizing a set of test configurations used for testing an electronic circuit that includes latches. An example method includes receiving a test configuration that includes settings that initiate a set of predetermined input values and corresponding expected output values. The method also includes evaluating the test configuration by executing the electronic circuit according to the test configuration and recording parametric data during the execution, where the parametric data is representative of switching activity of the latches in the electronic circuit. The evaluation includes analyzing the parametric data to identify presence of a predetermined pattern in the switching activity and selecting the test configuration based on the predetermined pattern being absent/present in the switching activity.

Abstract: According to an embodiment of the present invention, a computer-implemented method for inserting diagnostic circuit elements in a scan chain of a chip may include creating, via a processor, a segment for each latch of a plurality of latches in the scan chain to create a plurality of adjacent and connected segments, merging, via the processor, the two adjacent and connected segments to form a super-segment comprising all latches contained in the two adjacent and connected segments based on the objective function, and inserting, via the processor, a logic circuit element between the super-segment and a segment that is adjacent and connected to the super-segment in the scan chain, where the logic circuit element allows diagnostic isolation of the scan chain super-segment.

Abstract: Techniques relate to dynamic complex fault model generation for diagnostics simulation and pattern generation. Inline fabrication parametric data is received, and the inline fabrication parametric data is a collection of physical measurements made on a device under test during a manufacturing fabrication of the device under test. A fault model of defects is generated according to the inline fabrication parametric data, where the fault model is based on a physical design of the device under test combined with the inline fabrication parametric data for the device under test. Test patterns are generated based on the fault model and the inline fabrication parametric data, such that the test patterns are configured to test the device under test in order to obtain results that are based on the inline fabrication parametric data. A simulation is run of the device under test using the results and the inline fabrication parametric data.

Abstract: A failing latch is identified on a chip including a plurality of latches with the failing latch receiving data propagated from a first set of test input latches. A diagnostic set of latches is determined which includes the failing latch and a set of related latches. The set of related latches each receives data propagated from at least one test input latch from the first set of test input latches. The set of related latches is identified from a related latches table. One or more tests are performed on the chip and test output data is collected from the diagnostic set of latches. The related latches table is created by tracing from a target latch.

Abstract: A method of masking scan channels in a semiconductor chip includes storing, in first and second memories of a first mask logic, first and second channel mask enable decodes for first and second masks that mask first and second scan channels of a circuit under test; receiving at least three channel enable signals on three respective enable pins to produce a channel mask enable encode; comparing the channel mask enable encode to the stored first and second enable decodes; and masking the first or second scan channel when the channel mask enable encode respectively matches the first or second channel mask enable decode.

Abstract: A tool for determining unknown sources in a circuit design for exclusion from logic built-in self test (LBIST) verification for the circuit. The tool initializes, by one or more computer processors, one or more nets contained in an initial nets list, wherein the initial nets list is a representation of a circuit design being tested. The tool removes, by one or more computer processors, the one or more nets initialized in response to initialization of each of one or more latches in one or more test channels of the circuit design being tested. The tool determines, by one or more computer processors, whether a latch of the one or more latches is corrupted by an unknown source.

Abstract: A failing latch is identified on a chip including a plurality of latches with the failing latch receiving data propagated from a first set of test input latches. A diagnostic set of latches is determined which includes the failing latch and a set of related latches. The set of related latches each receives data propagated from at least one test input latch from the first set of test input latches. The set of related latches is identified from a related latches data source. One or more tests are performed on the chip and test output data is collected from the diagnostic set of latches. A related latches table may be created by tracing from a target latch.

Abstract: A semiconductor chip includes a first mask logic. The first mask logic includes a first mask and a second mask that mask a respective first scan channel output and a second scan channel output. The first mask logic includes at least three enable pins that receive respective enable signals. The three enable signals produce a channel mask enable encode. The first mask logic includes a first memory that stores a first channel mask enable decode for the first mask and a second memory that stores a second channel mask enable decode for the second mask. The first mask logic includes a first comparator and a second comparator. The first and second comparator compare the respective channel mask enable decodes to the channel mask enable encode. The comparators signal respective masks to mask the respective scan channel when the respective channel mask enable decode matches the channel mask enable encode.

Abstract: A method and circuits for implementing multiple input signature register (MISR) compression for test time reduction, and a design structure on which the subject circuits reside are provided. The MISR compression circuit includes a first MISR, a second MISR provided with the first MISR, and a compressor to compress MISR data positioned in one of between the first MISR and second MISR and after the second MISR.

Abstract: Embodiments relate to design-based weighting for logic built-in self-test (LBIST). An aspect includes an integrated circuit development system for implementing design-based weighting for LBIST. The system includes a memory system to create an integrated circuit layout. A processing circuit is coupled to the memory system. The processing circuit is configured to execute integrated circuit development tools to perform a method. The method includes analyzing, by the processing circuit, a plurality of integrated circuit design organizational units to determine preferred weightings of the integrated circuit design organizational units that provide a highest level of failure coverage when applied to a random pattern generator. Based on determining the preferred weightings, the processing circuit creates an integrated circuit layout that includes a plurality of weighted test paths to respectively apply the preferred weightings to the integrated circuit design organizational units.

Abstract: Embodiments relate to design-based weighting for logic built-in self-test (LBIST). An aspect includes a computer program product for implementing design-based weighting for LBIST. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes analyzing, by the processing circuit, a plurality of integrated circuit design organizational units to determine preferred weightings of the integrated circuit design organizational units that provide a highest level of failure coverage when applied to a random pattern generator. Based on determining the preferred weightings, the processing circuit creates an integrated circuit layout that includes a plurality of weighted test paths to respectively apply the preferred weightings to the integrated circuit design organizational units. The integrated circuit layout is incorporated in a device under test.

Abstract: A system and method of a test structure for testing a chip is disclosed. The system may include a scan channel comprising a plurality of scannable latches. The scan channel may be configured to scan input data to apply to logic circuits on a chip and further configured to receive outputs from logic circuits on the chip. The system may further include, a storage configured to store unmodified a selected bit of the scan channel during a scan out of the scan channel.

Abstract: A tool for determining unknown sources in a circuit design for exclusion from logic built-in self test (LBIST) verification for the circuit. The tool determines, by one or more computer processors, an initial nets list, wherein the initial nets list is a representation of a circuit design being tested. The tool initializes, by one or more computer processors, one or more nets contained in the initial nets list. The tool removes, by one or more computer processors, the one or more nets initialized in response to initialization of each of one or more latches in one or more test channels of the circuit design being tested. The tool determines, by one or more computer processors, whether a latch of the one or more latches is corrupted by an unknown source.

Abstract: First and second scan channels each comprise a plurality of scannable latches that apply input to and receive output from logic circuits on a chip under test. First input is scanned into the first scan channel and second input is scanned into the second scan channel. Output from the first scan channel is hashed using a first XOR on the first scan channel and output from the second scan channel is hashed using a first XOR on the second scan channel. Output from the first XOR on the first scan channel is hashed using a second XOR on the first scan channel. A rotator creates adjustment data from the output from the second XOR on the first scan channel. The adjustment data and output from the first XOR on the second scan channel are hashed using a second XOR on the second scan channel.

Abstract: A method of creating a scan pattern test file for testing hierarchal test blocks (HTBs) of scan channels on a semiconductor chip is described. The method includes determining a maximum number of channel mask enable encodes on the semiconductor chip. A maximum number of channel mask enable encodes used for the first HTB and the second HTB are determined. A plurality of test patterns used to test the first and the second HTB into one or more mask sets dependent on the number of masks each test pattern needs are sorted. The test patterns of the mask sets of the first and second HTB to be performed in a same test pattern are combined. The number of masks per scan cycle of the combined mask sets is no more than the maximum number of channel mask enable encodes on the semiconductor chip and there is no scan slice overlap.

Abstract: A method of creating a scan pattern test file for testing hierarchal test blocks (HTBs) of scan channels on a semiconductor chip is described. The method includes determining a maximum number of channel mask enable encodes on the semiconductor chip. A maximum number of channel mask enable encodes used for the first HTB and the second HTB are determined. A plurality of test patterns used to test the first and the second HTB into one or more mask sets dependent on the number of masks each test pattern needs are sorted. The test patterns of the mask sets of the first and second HTB to be performed in a same test pattern are combined. The number of masks per scan cycle of the combined mask sets is no more than the maximum number of channel mask enable encodes on the semiconductor chip and there is no scan slice overlap.