Patents by Inventor Masaaki Higuchi

Masaaki Higuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9831180
    Abstract: According to the embodiment, the semiconductor device includes: a substrate; a stacked body; and a plurality of columnar portions. The stacked body is provided on the substrate. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The stacked body includes a stacked portion and a staircase portion. The plurality of electrode layers includes a first portion and a second portion. The columnar portions are provided in the stacked portion of the stacked body. The columnar portions extend in a stacking direction of the stacked body. The columnar portions include a semiconductor body extending in the stacking direction and a charge storage film. The second portion includes a third portion. A thickness of the third portion along the stacking direction is thinner than a thickness of the first portion along the stacking direction.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: November 28, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masao Shingu, Kenta Yamada, Masaaki Higuchi, Daigo Ichinose
  • Patent number: 9786678
    Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises a plurality of conductive layers stacked in a first direction via an inter-layer insulating layer. In addition, the nonvolatile semiconductor memory device comprises: a semiconductor layer having the first direction as a longer direction; a tunnel insulating layer contacting a side surface of the semiconductor layer; a charge accumulation layer contacting a side surface of the tunnel insulating layer; and a block insulating layer contacting a portion facing the conductive layer, of a side surface of the charge accumulation layer. Moreover, the portion facing the conductive layer, of the charge accumulation layer is thinner compared to a portion facing the inter-layer insulating layer, of the charge accumulation layer.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: October 10, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Katsuyuki Sekine, Masaaki Higuchi, Masao Shingu, Hirokazu Ishigaki, Naoki Yasuda
  • Publication number: 20170271527
    Abstract: A semiconductor memory device includes a substrate, a multi-layered structure including a plurality of insulating layers and a plurality of conductive layers that are alternately formed above the substrate, and a pillar extending through the multi-layered structure. The pillar includes a semiconductor body extending along the pillar, and a charge-storing film around the semiconductor body, the charge-storing film having a first thickness at first portions facing the insulating layers and a second thickness greater than the first thickness at second portions facing the conductive layers.
    Type: Application
    Filed: September 29, 2016
    Publication date: September 21, 2017
    Inventors: Masaaki HIGUCHI, Masao SHINGU, Tatsuya KATO, Takeshi MURATA, Makoto FUJIWARA, Masaki KONDO, Muneyuki TSUDA, Takashi KURUSU
  • Publication number: 20170263558
    Abstract: According to the embodiment, the semiconductor device includes: a substrate; a stacked body; and a plurality of columnar portions. The stacked body is provided on the substrate. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The stacked body includes a stacked portion and a staircase portion. The plurality of electrode layers includes a first portion and a second portion. The columnar portions are provided in the stacked portion of the stacked body. The columnar portions extend in a stacking direction of the stacked body. The columnar portions include a semiconductor body extending in the stacking direction and a charge storage film. The second portion includes a third portion. A thickness of the third portion along the stacking direction is thinner than a thickness of the first portion along the stacking direction.
    Type: Application
    Filed: September 16, 2016
    Publication date: September 14, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masao Shingu, Kenta Yamada, Masaaki Higuchi, Daigo Ichinose
  • Patent number: 9754954
    Abstract: According to one embodiment, a non-volatile memory device includes a plurality of electrodes, at least one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film contacts the conductive layers, and extends in the first direction along the semiconductor layer between the conductive layers and the semiconductor layer. The second insulating film is provided between the first insulating film and the semiconductor layer. The first insulating film includes a first portion located between the conductive layers and the second insulating film, and a second portion located between the interlayer insulating film and the second insulating film.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: September 5, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masaaki Higuchi, Katsuyuki Sekine, Fumiki Aiso, Takuo Ohashi, Tatsuya Okamoto
  • Publication number: 20170243873
    Abstract: According to an embodiment, a semiconductor memory device comprises: a stacked body including control gate electrodes stacked upwardly of a substrate; a semiconductor layer facing the control gate electrodes; and a gate insulating layer provided between the control gate electrode and the semiconductor layer. The stacked body comprises: a first metal layer configuring the control gate electrode; a first barrier metal layer contacting an upper surface of this first metal layer; a first silicon nitride layer contacting an upper surface of this first barrier metal layer; a first inter-layer insulating layer contacting an upper surface of this first silicon nitride layer; a second barrier metal layer contacting a lower surface of the first metal layer; a second silicon nitride layer contacting a lower surface of this second barrier metal layer; and a second inter-layer insulating layer contacting a lower surface of this second silicon nitride layer.
    Type: Application
    Filed: September 19, 2016
    Publication date: August 24, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shigeki KOBAYASHI, Satoshi KONAGAI, Atsushi KONNO, Kenta YAMADA, Masaaki HIGUCHI, Masao SHINGU, Soichiro KITAZAKI, Yoshimasa MIKAJIRI
  • Publication number: 20170117293
    Abstract: According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film. The memory film includes a first portion formed between the stacked body and the semiconductor film and a second portion formed between the second layer and the semiconductor film. An outer periphery of the second portion in a plane perpendicular to the extending direction is wider than an outer periphery of the first portion on a second layer side of the stacked body.
    Type: Application
    Filed: January 4, 2017
    Publication date: April 27, 2017
    Inventors: Masaaki HIGUCHI, Masaru KITO, Masao SHINGU
  • Publication number: 20170069647
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer; an electrode layer; a first insulating film; a charge storage film; and a second insulating film. The first insulating film is provided between the electrode layer and the semiconductor layer. The charge storage film is provided between the first insulating film and the electrode layer. The charge storage film includes a charge trapping layer and a floating electrode layer. The floating electrode layer includes doped silicon. The second insulating film is provided between the floating electrode layer and the electrode layer.
    Type: Application
    Filed: March 7, 2016
    Publication date: March 9, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takuo OHASHI, Masaaki HIGUCHI
  • Patent number: 9583504
    Abstract: According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film. The memory film includes a first portion formed between the stacked body and the semiconductor film and a second portion formed between the second layer and the semiconductor film. An outer periphery of the second portion in a plane perpendicular to the extending direction is wider than an outer periphery of the first portion on a second layer side of the stacked body.
    Type: Grant
    Filed: March 2, 2014
    Date of Patent: February 28, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaaki Higuchi, Masaru Kito, Masao Shingu
  • Publication number: 20160315092
    Abstract: According to one embodiment, a non-volatile memory device includes a plurality of electrodes, at least one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film contacts the conductive layers, and extends in the first direction along the semiconductor layer between the conductive layers and the semiconductor layer. The second insulating film is provided between the first insulating film and the semiconductor layer. The first insulating film includes a first portion located between the conductive layers and the second insulating film, and a second portion located between the interlayer insulating film and the second insulating film.
    Type: Application
    Filed: July 5, 2016
    Publication date: October 27, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaaki HIGUCHI, Katsuyuki SEKINE, Fumiki AISO, Takuo OHASHI, Tatsuya OKAMOTO
  • Patent number: 9406691
    Abstract: According to one embodiment, a non-volatile memory device includes a plurality of electrodes, at least one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film contacts the conductive layers, and extends in the first direction along the semiconductor layer between the conductive layers and the semiconductor layer. The second insulating film is provided between the first insulating film and the semiconductor layer. The first insulating film includes a first portion located between the conductive layers and the second insulating film, and a second portion located between the interlayer insulating film and the second insulating film.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: August 2, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaaki Higuchi, Katsuyuki Sekine, Fumiki Aiso, Takuo Ohashi, Tatsuya Okamoto
  • Patent number: 9406811
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device including a semiconductor layer with a main surface, a first insulating layer formed on the main surface of the semiconductor layer, a charge storage layer formed on the first insulating layer, a second insulating layer formed on the charge storage layer, and a control gate electrode formed on the second insulating layer. At least one inelastic scattering film that reduces energy of electrons by scattering is contained in at least one of the charge storage layer and second insulating layer.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: August 2, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaaki Higuchi, Yoshio Ozawa, Katsuyuki Sekine, Ryota Fujitsuka
  • Publication number: 20160197094
    Abstract: According to one embodiment, a non-volatile memory device includes electrodes, one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film extends between the conductive layers and the semiconductor layer in the first direction. The second insulating film is provided between each electrode and the conductive layers. The conductive layers become smaller in a thickness as the conductive layers are closer to an end in the first direction or a direction opposite to the first direction. The second insulating film includes a first film contacting the conductive layers, and a second film provided between each electrode and the first film.
    Type: Application
    Filed: March 17, 2016
    Publication date: July 7, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaaki HIGUCHI, Katsuyuki SEKINE, Makoto FUJIWARA
  • Patent number: 9324729
    Abstract: According to one embodiment, a non-volatile memory device includes electrodes, one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film extends between the conductive layers and the semiconductor layer in the first direction. The second insulating film is provided between each electrode and the conductive layers. The conductive layers become smaller in a thickness as the conductive layers are closer to an end in the first direction or a direction opposite to the first direction. The second insulating film includes a first film contacting the conductive layers, and a second film provided between each electrode and the first film.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: April 26, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaaki Higuchi, Katsuyuki Sekine, Makoto Fujiwara
  • Publication number: 20160079269
    Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises a plurality of conductive layers stacked in a first direction via an inter-layer insulating layer. In addition, the nonvolatile semiconductor memory device comprises: a semiconductor layer having the first direction as a longer direction; a tunnel insulating layer contacting a side surface of the semiconductor layer; a charge accumulation layer contacting a side surface of the tunnel insulating layer; and a block insulating layer contacting a portion facing the conductive layer, of a side surface of the charge accumulation layer. Moreover, the portion facing the conductive layer, of the charge accumulation layer is thinner compared to a portion facing the inter-layer insulating layer, of the charge accumulation layer.
    Type: Application
    Filed: July 14, 2015
    Publication date: March 17, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsuyuki SEKINE, Masaaki Higuchi, Masao Shingu, Hirokazu Ishigaki, Naoki Yasuda
  • Publication number: 20160079257
    Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises a plurality of conductive layers that are stacked in plurality in a first direction via an inter-layer insulating layer, that extend in a second direction which intersects the first direction, and that are disposed in plurality in a third direction which intersects the first direction and the second direction. In addition, the same nonvolatile semiconductor memory device comprises: a semiconductor layer that has the first direction as a longitudinal direction; a tunnel insulating layer that contacts a side surface of the semiconductor layer; a charge accumulation layer that contacts a side surface of the tunnel insulating layer; and a block insulating layer that contacts a side surface of the charge accumulation layer. Furthermore, in the same nonvolatile semiconductor memory device, an end in the third direction of the plurality of conductive layers is rounded.
    Type: Application
    Filed: September 3, 2015
    Publication date: March 17, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeshi SONEHARA, Takahiro HIRAI, Masaaki HIGUCHI, Takashi SHIMIZU
  • Publication number: 20160064408
    Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises: a plurality of conductive layers stacked in a first direction via an inter-layer insulating layer; a semiconductor layer having the first direction as a longer direction; a tunnel insulating layer contacting a side surface of the semiconductor layer; a charge accumulation layer contacting a side surface of the tunnel insulating layer; and a block insulating layer contacting a side surface of the charge accumulation layer. The inter-layer insulating layer comprises: a first silicon oxide layer; a first metal oxide layer; and a first silicon nitride layer. The first metal oxide layer is formed on a first surface facing the conductive layer, of the first silicon oxide layer. The first silicon nitride layer is formed on the first surface via the first metal oxide layer.
    Type: Application
    Filed: July 22, 2015
    Publication date: March 3, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masao SHINGU, Masaaki HIGUCHI, Katsuyuki SEKINE, Kazuhiro MATSUO
  • Patent number: 9240416
    Abstract: A semiconductor memory device according to an embodiment includes a stacked body with electrode films and inter-electrode insulating films alternately stacked therein, a semiconductor member, a charge accumulation film, an insulating member and a floating electrode member. The semiconductor member is provided in the stacked body. The insulating member is provided at a position opposed to the inter-electrode insulating film on a side surface of the charge accumulation film. The insulating member is divided for each of the inter-electrode insulating films. The floating electrode member is provided on a region of the side surface of the charge accumulation film not covered with the insulating member. The floating electrode member is in contact with the charge accumulation film. The floating electrode member is divided for each of the electrode films. The floating electrode member has higher conductivity than the charge accumulation film.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: January 19, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Shimura, Masaaki Higuchi, Hirokazu Ishigaki, Tatsuya Okamoto
  • Publication number: 20160013201
    Abstract: According to one embodiment, a non-volatile memory device includes a plurality of electrodes, at least one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film contacts the conductive layers, and extends in the first direction along the semiconductor layer between the conductive layers and the semiconductor layer. The second insulating film is provided between the first insulating film and the semiconductor layer. The first insulating film includes a first portion located between the conductive layers and the second insulating film, and a second portion located between the interlayer insulating film and the second insulating film.
    Type: Application
    Filed: September 24, 2015
    Publication date: January 14, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaaki HIGUCHI, Katsuyuki SEKINE, Fumiki AISO, Takuo OHASHI, Tatsuya OKAMOTO
  • Publication number: 20150372002
    Abstract: According to one embodiment, a non-volatile memory device includes electrodes, one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film extends between the conductive layers and the semiconductor layer in the first direction. The second insulating film is provided between each electrode and the conductive layers. The conductive layers become smaller in a thickness as the conductive layers are closer to an end in the first direction or a direction opposite to the first direction. The second insulating film includes a first film contacting the conductive layers, and a second film provided between each electrode and the first film.
    Type: Application
    Filed: September 11, 2014
    Publication date: December 24, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaaki HIGUCHI, Katsuyuki SEKINE, Makoto FUJIWARA