Patents by Inventor Masaaki Ishii

Masaaki Ishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200233535
    Abstract: A wiring body includes: a resin portion; and a conductor portion disposed on the resin portion and that has a mesh shape in which first conductor wires and second conductor wires intersect with one another. The conductor portion includes a wide portion disposed to correspond to an intersection portion where one of the first conductor wires intersects with one of the second conductor wires, and following Formula (1) is satisfied: 6<Sc/(La×Lb)?30 . . . (1) where Sc is an area of the wide portion, La is a width of one of the first conductor wires, and Lb is a width of one of the second conductor wires.
    Type: Application
    Filed: March 26, 2018
    Publication date: July 23, 2020
    Applicant: FUJIKURA LTD.
    Inventors: Takeshi Shiojiri, Masaaki Ishii
  • Publication number: 20200127458
    Abstract: In a power storage system, a three-phase AC wire is connected to a three-phase AC power system. Power storage blocks, each of which includes a power storage module and a power conditioner, are connected in parallel to the three-phase AC wire. A system controller individually controls power storage blocks. The power storage modules each includes: a power storage unit; and a management unit that manages the power storage unit. The power conditioner includes a power converter and a controller. The power converter converts DC power discharged into single-phase AC power and outputs the converted AC power to two lines of the three-phase AC wire, or converts single-phase AC power received from the two lines of the three-phase AC wire into DC power and charges the power storage unit. The controller is connected to the system controller via a communication line and the management unit via a communication line.
    Type: Application
    Filed: April 16, 2018
    Publication date: April 23, 2020
    Inventors: MASAKI KATO, NAOHISA MORIMOTO, MASAAKI KURANUKI, JUN YAMASAKI, YOHEI ISHII, KOICHI SAWADA
  • Publication number: 20200115327
    Abstract: An isocyanate production method according to the present invention is a method in which an isocyanate is produced by subjecting a carbamate to thermal decomposition, and includes: a step of preparing a mixture liquid containing the carbamate, an inactive solvent and a polyisocyanate compound; a step of conducting a thermal decomposition reaction of the carbamate by continuously introducing the mixture liquid into a thermal decomposition reactor; a step of collecting a low-boiling decomposition product by continuously extracting the low-boiling decomposition product in a gaseous state from the reactor, the low-boiling decomposition product having a boiling point lower than the polyisocyanate compound; and a step of collecting a high-boiling component by continuously extracting, from the reactor, a liquid phase component which is not collected in a gaseous state at the step of collecting the low-boiling decomposition product.
    Type: Application
    Filed: May 15, 2018
    Publication date: April 16, 2020
    Applicant: ASAHI KASEI KABUSHIKI KAISHA
    Inventors: Nobuhisa MIYAKE, Koichi NAKAOKA, Tsubasa UEMATSU, Yusuke SAKURAI, Yusuke ISHII, Kazuhiro TAKAGAKI, Takeharu SASAKI, Yuji KOSUGI, Atsushi OHKUBO, Masaaki SHINOHATA
  • Publication number: 20200057301
    Abstract: A cleaning device includes a casing holding an image capturing device, a protective cover disposed in a visual field of the image capturing device, a vibrator to vibrate the protective cover, a controller to control the vibrator, a monitor to detect an electrical characteristic value associated with a vibration of the vibrator, and a storage to store determination criteria based on which the controller evaluates the electrical characteristic value detected by the monitor. The controller is configured to evaluate the electrical characteristic value based on the plurality of determination criteria stored in the storage and clean a surface of the translucent body by controlling the vibrator according to the determination.
    Type: Application
    Filed: October 25, 2019
    Publication date: February 20, 2020
    Inventors: Yasuhiro KURATANI, Katsumi FUJIMOTO, Kenji NISHIYAMA, Chikahiro HORIGUCHI, Shinichiro ICHIGUCHI, Masaaki TAKATA, Yuzo MIZUSHIMA, Yuuki ISHII
  • Patent number: 10497500
    Abstract: A powder magnetic core having excellent specific resistance or strength. The powder magnetic core has soft magnetic particles, first coating layers that coat the surfaces of the soft magnetic particles and include aluminum nitride, and second coating layers that coat at least a part of the surfaces of the first coating layers and include a low-melting-point glass having a softening point lower than an annealing temperature for the soft magnetic particles. The first coating layers including aluminum nitride are excellent in the wettability to the low-melting-point glass which constitutes the second coating layers and suppress diffusion of constitutional elements between the soft magnetic particles and the low-melting-point glass of the second coating layers. The powder magnetic core can stably exhibit a higher specific resistance and higher strength than the prior art owing to such a synergistic action of the first coating layers and second coating layers.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: December 3, 2019
    Assignee: TOYOTA JIDOSHA KABUHIKI KAISHA
    Inventors: Masashi Ohtsubo, Masaaki Tani, Takeshi Hattori, Jung hwan Hwang, Masashi Hara, Shin Tajima, Naoki Iwata, Shinjiro Saigusa, Kohei Ishii, Daisuke Okamoto, Toshimitsu Takahashi
  • Publication number: 20190214172
    Abstract: A dust core includes soft magnetic particles, a first coating layer, a second coating layer, and a third coating layer. The first coating layer is made of aluminum oxide with which at least a part of surfaces of the soft magnetic particles are coated. The second coating layer is made of aluminum nitride with which at least a part of a surface of the first coating layer is coated. The third coating layer is made of low-melting-point glass with which at least a part of a surface of the second coating layer is coated. The low-melting-point glass has a softening point lower than an annealing temperature of the soft magnetic particles.
    Type: Application
    Filed: March 18, 2019
    Publication date: July 11, 2019
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masashi OHTSUBO, Masaaki TANI, Takeshi HATTORI, Junghwan HWANG, Masashi HARA, Shin TAJIMA, Shinjiro SAIGUSA, Kohei ISHII, Daisuke OKAMOTO, Toshimitsu TAKAHASHI
  • Publication number: 20190213363
    Abstract: An information reader includes a reader main unit and a case. The case houses therein an inner pad serving as an electrostatic capacity type of switch used by an operator to enable an information reading unit to read information. The inner pad is assembled within the case to be directed toward a touch detection region of the case. A switch unit, which is separated from the reader main unit, is provided with a touch electrode pad to which electrical charge is applied in response to an operator's touch operation, a wiring line one of whose both ends is electrically connected to the touch electrode pad, and a transmission pad to which the other end is electrically connected. The transmission pad is assembled with the case on the outer surface thereof.
    Type: Application
    Filed: October 26, 2018
    Publication date: July 11, 2019
    Applicant: DENSO WAVE INCORPORATED
    Inventors: Akihiro SUGIURA, Masaaki KURIYAMA, Koji KONOSU, Hiroshi HISHIDA, Hidenori ISHII, Yoshihiro YAMAZAKI
  • Patent number: 10300576
    Abstract: A polishing method including polishing to polish a surface of a wafer by sliding the wafer held by a polishing head on a surface of a polishing pad while supplying a polishing slurry to the polishing pad attached to a turntable, the method including correlation derivation to obtain a correlation between a surface temperature of the polishing pad and a haze level of a wafer polished with the use of the polishing pad in advance before performing the polishing, and also the wafer is polished in the polishing while controlling the surface temperature of the polishing pad based on the correlation between the surface temperature of the polishing pad and the haze level of the wafer polished with the use of the polishing pad. Consequently, the polishing method can control a haze in polishing a wafer and thereby prolong the service life of the polishing pad.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: May 28, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Masaaki Oseki, Michito Sato, Kaoru Ishii
  • Publication number: 20190050328
    Abstract: To prevent a bank conflict in a memory with respect to an access address interval of a wide range. In a plurality of memory modules, an address is provided in a circulation manner for each word. A plurality of access ports is input/output ports for accessing the plurality of memory modules. A plurality of address converting sections converts the address to rearrange an arrangement of the words in the plurality of memory modules by a transposing process for a square matrix of a predetermined size. A connecting section connects the plurality of memory modules and the plurality of access ports in accordance with a result of the address conversion.
    Type: Application
    Filed: January 23, 2017
    Publication date: February 14, 2019
    Inventors: MASAAKI ISHII, HIROAKI SAKAGUCHI
  • Publication number: 20180307344
    Abstract: A wiring body includes: a resin portion composed of a resin material and a linear conductor portion composed of a conductive material and disposed on the resin portion. The resin portion includes: a flat portion; a protruding portion disposed corresponding to the conductor portion and protrudes towards the conductor portion with respect to the flat portion; and a recessed portion disposed between the flat portion and the protruding portion and dented into a shape of a curve in a direction away from the conductor portion with respect to the flat portion. The conductor portion includes: a contact surface in contact with the protruding portion and a top surface positioned on a side opposite to the contact surface. The top surface is parallel to the flat portion and a side surface of the protruding portion and the recessed portion are continuous.
    Type: Application
    Filed: October 19, 2016
    Publication date: October 25, 2018
    Applicant: FUJIKURA LTD.
    Inventor: Masaaki Ishii
  • Patent number: 10102132
    Abstract: Data transfer between processors is efficiently performed in a multiprocessor including a shared cache memory. Each entry in a tag storage section 220 of a cache memory holds a reference number field 224 in addition to a tag address field 221, a valid field 222, and a dirty field 223. The reference number field 224 is set in a data write, and the value thereof is decremented after each read access. When the value of the reference number field 224 is changed from “1” to “0”, the entry is invalidated without performing a write-back operation. When the cache memory is used for communication between processors in the multiprocessor system, the cache memory functions as a shared FIFO, and used data is automatically deleted.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: October 16, 2018
    Assignee: SONY CORPORATION
    Inventors: Taichi Hirao, Hiroaki Sakaguchi, Hiroshi Yoshikawa, Masaaki Ishii
  • Publication number: 20170293382
    Abstract: A wiring body includes an adhesive layer and a mesh-like electrode layer having a shape of a mesh formed by fine wires intersecting each other is formed on the adhesive layer. The mesh-like electrode layer includes an intersection region intersecting the fine wires with each other and a non-intersection region corresponding to a region except for the intersection region. A depression recessed toward the adhesive layer is formed in the intersection region.
    Type: Application
    Filed: April 28, 2016
    Publication date: October 12, 2017
    Applicant: FUJIKURA LTD.
    Inventor: Masaaki Ishii
  • Publication number: 20170083440
    Abstract: Data transfer between processors is efficiently performed in a multiprocessor including a shared cache memory. Each entry in a tag storage section 220 of a cache memory holds a reference number field 224 in addition to a tag address field 221, a valid field 222, and a dirty field 223. The reference number field 224 is set in a data write, and the value thereof is decremented after each read access. When the value of the reference number field 224 is changed from “1” to “0”, the entry is invalidated without performing a write-back operation. When the cache memory is used for communication between processors in the multiprocessor system, the cache memory functions as a shared FIFO, and used data is automatically deleted.
    Type: Application
    Filed: November 30, 2016
    Publication date: March 23, 2017
    Inventors: TAICHI HIRAO, HIROAKI SAKAGUCHI, HIROSHI YOSHIKAWA, MASAAKI ISHII
  • Patent number: 9535841
    Abstract: Data transfer between processors is efficiently performed in a multiprocessor including a shared cache memory. Each entry in a tag storage section 220 of a cache memory holds a reference number field 224 in addition to a tag address field 221, a valid field 222, and a dirty field 223. The reference number field 224 is set in a data write, and the value thereof is decremented after each read access. When the value of the reference number field 224 is changed from “1” to “0”, the entry is invalidated without performing a write-back operation. When the cache memory is used for communication between processors in the multiprocessor system, the cache memory functions as a shared FIFO, and used data is automatically deleted.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: January 3, 2017
    Assignee: SONY CORPORATION
    Inventors: Taichi Hirao, Hiroaki Sakaguchi, Hiroshi Yoshikawa, Masaaki Ishii
  • Patent number: 9212881
    Abstract: In a hole examining device, an examination head (105) is supported to be movable in an X direction and a Y direction which are orthogonal to each other, measurement heads (125, 126) are supported to be movable in a Z direction which is orthogonal to the X direction and the Y direction with respect to the examination head (105), and a plurality of first measurers (127) and a plurality of second measurers (128) are arranged in the measurement heads (125, 126) in parallel and may be held at an advance position which advances as well as retreats with respect to the Z direction, thereby improving workability of an examining operation.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: December 15, 2015
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Yoshitake Kasubata, Masaaki Ishii
  • Publication number: 20130192076
    Abstract: In a hole examining device, an examination head (105) is supported to be movable in an X direction and a Y direction which are orthogonal to each other, measurement heads (125, 126) are supported to be movable in a Z direction which is orthogonal to the X direction and the Y direction with respect to the examination head (105), and a plurality of first measurers (127) and a plurality of second measurers (128) are arranged in the measurement heads (125, 126) in parallel and may be held at an advance position which advances as well as retreats with respect to the Z direction, thereby improving workability of an examining operation.
    Type: Application
    Filed: November 8, 2011
    Publication date: August 1, 2013
    Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Yoshitake Kasubata, Masaaki Ishii
  • Publication number: 20120331234
    Abstract: Data transfer between processors is efficiently performed in a multiprocessor including a shared cache memory. Each entry in a tag storage section 220 of a cache memory holds a reference number field 224 in addition to a tag address field 221, a valid field 222, and a dirty field 223. The reference number field 224 is set in a data write, and the value thereof is decremented after each read access. When the value of the reference number field 224 is changed from “1” to “0”, the entry is invalidated without performing a write-back operation. When the cache memory is used for communication between processors in the multiprocessor system, the cache memory functions as a shared FIFO, and used data is automatically deleted.
    Type: Application
    Filed: December 14, 2010
    Publication date: December 27, 2012
    Applicant: Sony Corporation
    Inventors: Taichi Hirao, Hiroaki Sakaguchi, Hiroshi Yoshikawa, Masaaki Ishii
  • Patent number: 8245015
    Abstract: A processor includes a plurality of executing sections configured to simultaneously execute instructions for a plurality of threads, an instruction issuing section configured to issue instructions to the plurality of executing sections, and an instruction sync monitoring section configured to, when an instruction-synchronizing instruction is issued to one or more of the plurality of executing sections from the instruction issuing section, monitor completion of execution of the instruction-synchronizing instruction for each of the executing sections, to which the instruction-synchronizing instruction has been issued, thus detecting completion of execution of preceding instructions for the thread to which the instruction-synchronizing instruction belongs.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: August 14, 2012
    Assignee: Sony Corporation
    Inventor: Masaaki Ishii
  • Patent number: 7949696
    Abstract: Disclosed herein is a floating-point number arithmetic circuit for efficiently supplying data to be performed arithmetic operation. The floating-point number arithmetic circuit includes an floating-point number arithmetic unit for performing a predetermined floating-point number arithmetic operation on a floating-point number of a predetermined precision, and a converting circuit for converting data into the floating-point number of predetermined precision and supplying the floating-point number of the predetermined precision to at least either one of input terminals of the floating-point number arithmetic unit.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: May 24, 2011
    Assignee: Sony Corporation
    Inventors: Masaaki Ishii, Koichi Hasegawa, Hiroaki Sakaguchi
  • Publication number: 20100011195
    Abstract: A processor includes a plurality of executing sections configured to simultaneously execute instructions for a plurality of threads, an instruction issuing section configured to issue instructions to the plurality of executing sections, and an instruction sync monitoring section configured to, when an instruction-synchronizing instruction is issued to one or more of the plurality of executing sections from the instruction issuing section, monitor completion of execution of the instruction-synchronizing instruction for each of the executing sections, to which the instruction-synchronizing instruction has been issued, thus detecting completion of execution of preceding instructions for the thread to which the instruction-synchronizing instruction belongs.
    Type: Application
    Filed: July 7, 2009
    Publication date: January 14, 2010
    Applicant: Sony Corporation
    Inventor: Masaaki Ishii