Abstract: Provided is a film-covered transparent base plate having an excellent aesthetic appearance even during turn-off of a light source. A film-covered transparent base plate 1 includes a transparent base plate 2 and a light-absorbing film 3 provided on one principal surface 2a of the transparent base plate 2 and the light-absorbing film 3 includes a dielectric phase made of a material having a band gap of not less than 2.0 eV and not more than 2.7 eV and a metallic phase.

Abstract: A delta-sigma modulation apparatus performs delta-sigma modulation on a first signal as an input signal and outputs a second signal, outputs, using the second signal and a third signal generated through a transmission process of the second signal, a fourth signal that is an approximated value of a signal which is generated through at least part of the transmission process, and performs the delta-sigma modulation on the first signal using the fourth signal and outputs the second signal.

Abstract: Provided is a concentration measurement device that can be miniaturized without using an optical fiber. The concentration measurement device including a measurement cell having a gas flow path and an optical path intersecting the gas flow path; a light source for emitting light inside the optical path, the light source 14 being installed at one end of the optical path; a first photodetector for detecting a light emitted from the light source as a reference light, the first photodetector being installed at a side of the light source and rearward from a distal end of the light source in a light emitting direction along an optical axis of the light source; a second photodetector for detecting a light emitted from the light source for measuring light absorption, the second photodetector being installed at another end of the optical path.

Abstract: The present technology relates to an information processing apparatus, an information processing method, and a program capable of improving the efficiency and accuracy of clustering. The information processing apparatus estimates a presence area of an object and the number of objects on the basis of a captured image, generates point cloud data from distance measurement information acquired by a distance measuring sensor, and recognizes the object by determining a point cloud, which is a target of clustering, in the point cloud data generated and the number of clusters on the basis of the presence area of the object and the number of the objects, which are estimated, and performing clustering on the point cloud data. The present technology can be applied to an autonomous mobile robot system.

Abstract: To realize a depthwise, pointwise separable convolution (DPSC) operation without increasing a memory size and reduce the number of parameters and the amount of operation in a convolutional layer. This arithmetic operation device includes a first product-sum operator, a second product-sum operator, and a cumulative unit. The first product-sum operator performs a product-sum operation of input data and a first weight. The second product-sum operator is connected to an output portion of the first product-sum operator, and performs a product-sum operation of the output of the first product-sum operator and a second weight. The cumulative unit sequentially adds the output of the second product-sum operator.

Abstract: To prevent a bank conflict in a memory with respect to an access address interval of a wide range. In a plurality of memory modules, an address is provided in a circulation manner for each word. A plurality of access ports is input/output ports for accessing the plurality of memory modules. A plurality of address converting sections converts the address to rearrange an arrangement of the words in the plurality of memory modules by a transposing process for a square matrix of a predetermined size. A connecting section connects the plurality of memory modules and the plurality of access ports in accordance with a result of the address conversion.

Abstract: A wiring body includes: a resin portion; and a conductor portion disposed on the resin portion and that has a mesh shape in which first conductor wires and second conductor wires intersect with one another. The conductor portion includes a wide portion disposed to correspond to an intersection portion where one of the first conductor wires intersects with one of the second conductor wires, and following Formula (1) is satisfied: 6<Sc/(La×Lb)?30 . . . (1) where Sc is an area of the wide portion, La is a width of one of the first conductor wires, and Lb is a width of one of the second conductor wires.

Abstract: To prevent a bank conflict in a memory with respect to an access address interval of a wide range. In a plurality of memory modules, an address is provided in a circulation manner for each word. A plurality of access ports is input/output ports for accessing the plurality of memory modules. A plurality of address converting sections converts the address to rearrange an arrangement of the words in the plurality of memory modules by a transposing process for a square matrix of a predetermined size. A connecting section connects the plurality of memory modules and the plurality of access ports in accordance with a result of the address conversion.

Abstract: A wiring body includes: a resin portion composed of a resin material and a linear conductor portion composed of a conductive material and disposed on the resin portion. The resin portion includes: a flat portion; a protruding portion disposed corresponding to the conductor portion and protrudes towards the conductor portion with respect to the flat portion; and a recessed portion disposed between the flat portion and the protruding portion and dented into a shape of a curve in a direction away from the conductor portion with respect to the flat portion. The conductor portion includes: a contact surface in contact with the protruding portion and a top surface positioned on a side opposite to the contact surface. The top surface is parallel to the flat portion and a side surface of the protruding portion and the recessed portion are continuous.

Abstract: Data transfer between processors is efficiently performed in a multiprocessor including a shared cache memory. Each entry in a tag storage section 220 of a cache memory holds a reference number field 224 in addition to a tag address field 221, a valid field 222, and a dirty field 223. The reference number field 224 is set in a data write, and the value thereof is decremented after each read access. When the value of the reference number field 224 is changed from “1” to “0”, the entry is invalidated without performing a write-back operation. When the cache memory is used for communication between processors in the multiprocessor system, the cache memory functions as a shared FIFO, and used data is automatically deleted.

Abstract: A wiring body includes an adhesive layer and a mesh-like electrode layer having a shape of a mesh formed by fine wires intersecting each other is formed on the adhesive layer. The mesh-like electrode layer includes an intersection region intersecting the fine wires with each other and a non-intersection region corresponding to a region except for the intersection region. A depression recessed toward the adhesive layer is formed in the intersection region.

Abstract: Data transfer between processors is efficiently performed in a multiprocessor including a shared cache memory. Each entry in a tag storage section 220 of a cache memory holds a reference number field 224 in addition to a tag address field 221, a valid field 222, and a dirty field 223. The reference number field 224 is set in a data write, and the value thereof is decremented after each read access. When the value of the reference number field 224 is changed from “1” to “0”, the entry is invalidated without performing a write-back operation. When the cache memory is used for communication between processors in the multiprocessor system, the cache memory functions as a shared FIFO, and used data is automatically deleted.

Abstract: Data transfer between processors is efficiently performed in a multiprocessor including a shared cache memory. Each entry in a tag storage section 220 of a cache memory holds a reference number field 224 in addition to a tag address field 221, a valid field 222, and a dirty field 223. The reference number field 224 is set in a data write, and the value thereof is decremented after each read access. When the value of the reference number field 224 is changed from “1” to “0”, the entry is invalidated without performing a write-back operation. When the cache memory is used for communication between processors in the multiprocessor system, the cache memory functions as a shared FIFO, and used data is automatically deleted.

Abstract: In a hole examining device, an examination head (105) is supported to be movable in an X direction and a Y direction which are orthogonal to each other, measurement heads (125, 126) are supported to be movable in a Z direction which is orthogonal to the X direction and the Y direction with respect to the examination head (105), and a plurality of first measurers (127) and a plurality of second measurers (128) are arranged in the measurement heads (125, 126) in parallel and may be held at an advance position which advances as well as retreats with respect to the Z direction, thereby improving workability of an examining operation.

Abstract: In a hole examining device, an examination head (105) is supported to be movable in an X direction and a Y direction which are orthogonal to each other, measurement heads (125, 126) are supported to be movable in a Z direction which is orthogonal to the X direction and the Y direction with respect to the examination head (105), and a plurality of first measurers (127) and a plurality of second measurers (128) are arranged in the measurement heads (125, 126) in parallel and may be held at an advance position which advances as well as retreats with respect to the Z direction, thereby improving workability of an examining operation.

Abstract: Data transfer between processors is efficiently performed in a multiprocessor including a shared cache memory. Each entry in a tag storage section 220 of a cache memory holds a reference number field 224 in addition to a tag address field 221, a valid field 222, and a dirty field 223. The reference number field 224 is set in a data write, and the value thereof is decremented after each read access. When the value of the reference number field 224 is changed from “1” to “0”, the entry is invalidated without performing a write-back operation. When the cache memory is used for communication between processors in the multiprocessor system, the cache memory functions as a shared FIFO, and used data is automatically deleted.

Abstract: A processor includes a plurality of executing sections configured to simultaneously execute instructions for a plurality of threads, an instruction issuing section configured to issue instructions to the plurality of executing sections, and an instruction sync monitoring section configured to, when an instruction-synchronizing instruction is issued to one or more of the plurality of executing sections from the instruction issuing section, monitor completion of execution of the instruction-synchronizing instruction for each of the executing sections, to which the instruction-synchronizing instruction has been issued, thus detecting completion of execution of preceding instructions for the thread to which the instruction-synchronizing instruction belongs.

Abstract: Disclosed herein is a floating-point number arithmetic circuit for efficiently supplying data to be performed arithmetic operation. The floating-point number arithmetic circuit includes an floating-point number arithmetic unit for performing a predetermined floating-point number arithmetic operation on a floating-point number of a predetermined precision, and a converting circuit for converting data into the floating-point number of predetermined precision and supplying the floating-point number of the predetermined precision to at least either one of input terminals of the floating-point number arithmetic unit.

Abstract: A processor includes a plurality of executing sections configured to simultaneously execute instructions for a plurality of threads, an instruction issuing section configured to issue instructions to the plurality of executing sections, and an instruction sync monitoring section configured to, when an instruction-synchronizing instruction is issued to one or more of the plurality of executing sections from the instruction issuing section, monitor completion of execution of the instruction-synchronizing instruction for each of the executing sections, to which the instruction-synchronizing instruction has been issued, thus detecting completion of execution of preceding instructions for the thread to which the instruction-synchronizing instruction belongs.

Abstract: Disclosed herein is a floating-point number arithmetic circuit for efficiently supplying data to be performed arithmetic operation. The floating-point number arithmetic circuit includes an floating-point number arithmetic unit for performing a predetermined floating-point number arithmetic operation on a floating-point number of a predetermined precision, and a converting circuit for converting data into the floating-point number of predetermined precision and supplying the floating-point number of the predetermined precision to at least either one of input terminals of the floating-point number arithmetic unit.