Abstract: A field effect transistor (20) comprises a first semiconductor layer (24) and a second semiconductor layer (25) formed on the first semiconductor layer. The first semiconductor layer is an undoped layer and is composed of InGaAs. The second semiconductor layer is composed of InAlGaP and is a doped layer in which an n-type impurity is doped. A heterojunction structure is formed between the first semiconductor layer and the second semiconductor layer.

Abstract: In a field effect transistor having a channel layer interposed between heterojunctions, the channel layer has an intermediate layer of undoped InGaAs interposed between first and second channel layers each of which has a composition different from the intermediate layer. The composition of each of the first and the second channel layers may be composed of either InP or InGaAs. The intermediate layer may be formed either by a single layer of InGaAs or by a plurality of intermediate films of InGaAs which have In compositions different from one another when each of the first and the second channel layers is composed of InP. A maximum one of the In compositions is assigned to a selected one of the intermediate films. Alternatively, a selected one of the intermediate films includes a maximum In composition when each of the first and the second channel layers is formed by InGaAs.

Abstract: The invention provides a compound semiconductor multilayer structure having a two-dimensional electron gas, which is applicable to field effect transistors. A ternary compound InGaAs planar channel layer serving as a quantum well has a variation of an In (indium) fraction in a perpendicular direction to a heterojunction interface. The variation has a step-graded profile with taking a maximum value at or in the vicinity of a portion where the two-dimensional electron gas takes a maximum density. Such quantum well has most large depth at a portion except for adjacent portions to the heterojunction interfaces. Such multilayer structure provides a great electron mobility and a strong electron confinement to major electrons at a high electron density portion.

Abstract: An EEPROM cell is implemented by a field effect transistor comprising a channel layer of an intentionally undoped gallium arsenide, a carrier supplying layer formed on the channel layer and of a heavily doped n-type aluminum gallium arsenide having deep energy level, and a gate electrode formed on the carrier supplying layer, in which the deep energy level causes a current-voltage collapse phenomenon to take place due to trapping hot electrons injected from the channel layer to the carrier supplying layer in the presence of a stress voltage of about 1.2 volts between the source and drain for minimizing channel conductivity and in which the stress voltage of about 3 volts ionizes the deep energy level so as to allow recovering from the current-voltage collapse phenomenon, thereby providing the low and high channel conductivities to two logic levels.

Abstract: A quasi one-dimensional electron gas FET with semiconductor layer of a stripe structure formed on a semi-insulating semiconductor substrate. A gate electrode is formed traversing the exposed portions of the semiconductor substrate and the side faces and the upper face of the stripe structure, and a source electrode and a drain electrode are formed on the respective ends of the stripe structure with the gate electrode in between. The stripe structure consists of a potential barrier layer, an undoped channel layer and an electron supplying layer.