Patents by Inventor Masaaki Nakabayashi

Masaaki Nakabayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6599794
    Abstract: A method of manufacturing a semiconductor device comprising forming a sacrificial layer including one or more conductive film on a semiconductor substrate, forming a cavity used as a template of electroplating in the sacrificial layer, growing a metal film on a surface of the cavity by the electroplating using the conductive layer as a seed layer so that a cylindrical or convex electrode can be formed, and removing the sacrificial layer so that the electrode can be formed.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: July 29, 2003
    Assignees: Kabushiki Kaisha Toshiba, Fujitsu Limited
    Inventors: Masahiro Kiyotoshi, Kazuhiro Eguchi, Masaaki Nakabayashi, Fumihiko Inoue
  • Publication number: 20030112515
    Abstract: A diffractive optical element includes a blazed diffraction grating having inclined facets and vertical facets arrayed in an alternating sequence, in which only the vertical facets of the blazed diffraction grating are frosted by ashing. Another diffractive optical element includes a blazed diffraction grating having inclined facets and vertical facets arrayed in an alternating sequence, in which only the vertical facets of the blazed diffraction grating have an opaque film formed thereon.
    Type: Application
    Filed: November 1, 2002
    Publication date: June 19, 2003
    Inventor: Masaaki Nakabayashi
  • Publication number: 20030044728
    Abstract: A method of manufacturing a micro-structure having a plurality of step-like elements, includes the steps of etching a first region of a substrate, corresponding to a lowest step of the step-like element, with an appropriate depth, whereby a surface of the lowest step of the step-like element is defined, and etching, subsequently, a second region of the substrate, corresponding to another step of the step-like element, with an appropriate depth, whereby a surface of that step of the step-like element is defined.
    Type: Application
    Filed: September 17, 1999
    Publication date: March 6, 2003
    Inventors: JUNJI TERADA, MASAAKI NAKABAYASHI, SENICHI HAYASHI
  • Patent number: 6523963
    Abstract: The present invention provides a diffraction optical element comprising a first optical member having a first diffraction grating, a second optical member having a second diffraction grating, wherein the first and second optical members are stacked so that the first and second diffraction gratings face each other inside the stacked members and so that a space is formed between the diffraction gratings, and a sealing member for hermetically sealing the space between the diffraction gratings.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: February 25, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masaaki Nakabayashi
  • Patent number: 6522464
    Abstract: A diffraction optical element comprises a substrate, a diffraction grating formed on the substrate with a material with low ultraviolet resistance and an ultraviolet screening means arranged on the substrate at a position closer to the incident light receiving side of the optical element relative to the diffraction grating. The ultraviolet screening means comprises a dielectric multilayer film and is formed on the other side of the substrate than the side carrying the diffraction grating. Alternatively, the ultraviolet screening means may be provided as a separate member from a diffraction optical element and arranged at a position closer to the incident light receiving side of the diffraction optical element in an optical system.
    Type: Grant
    Filed: March 14, 2001
    Date of Patent: February 18, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tetsuo Kuwabara, Masaaki Nakabayashi
  • Publication number: 20030025223
    Abstract: The object of this invention is to provide a mold releasing method for a diffraction optical element, which enables stable mass production of a diffraction optical element free from deformation or damage due to mold release. In order to achieve this object, a mold releasing method for a diffraction optical element, of releasing from a mold a diffraction optical element formed by using the mold and having a convex lens function, includes the steps of pressing a central portion of the diffraction optical element toward the mold, and pushing a periphery of the diffraction optical element in a direction to separate from the mold, so that mold release progresses from the periphery toward the central portion of the diffraction optical element. The method also includes the step of adjusting the balance with a plurality of hydraulic cylinders without pressing the central portion, so that mold release progresses toward the center.
    Type: Application
    Filed: July 2, 2002
    Publication date: February 6, 2003
    Applicant: Canon Kabushiki Kaisha
    Inventor: Masaaki Nakabayashi
  • Patent number: 6515843
    Abstract: The present invention relates to semiconductor techniques using high dielectric oxides, more specifically to a thin film forming method for forming a thin film which is suitable as the electrodes of the oxide high dielectrics, a capacitor device using the oxide high dielectrics and a method for fabricating the same, an a semiconductor device using the capacitor device and a method for fabricating the semiconductor device. The capacitor device includes at least one of a pair of electrodes which is formed of a material containing titanium nitride of (200) orientation. This permits the capacitor device to have good quality even in a case that the capacitor dielectric film is formed of a high dielectric thin film grown in an oxidizing atmosphere. The capacitor device includes the electrodes of titanium nitride film, whereby the electrodes can be patterned by RIE, which much improves processing precision of the electrode patterning, and throughputs.
    Type: Grant
    Filed: October 2, 1998
    Date of Patent: February 4, 2003
    Assignee: Fujitsu Limited
    Inventors: Masaaki Nakabayashi, Tetsuro Tamura, Hideyuki Noshiro
  • Publication number: 20030017669
    Abstract: A method of manufacturing a semiconductor device comprising forming a sacrificial layer including one or more conductive film on a semiconductor substrate, forming a cavity used as a template of electroplating in the sacrificial layer, growing a metal film on a surface of the cavity by the electroplating using the conductive layer as a seed layer so that a cylindrical or convex electrode can be formed, and removing the sacrificial layer so that the electrode can be formed.
    Type: Application
    Filed: July 16, 2002
    Publication date: January 23, 2003
    Inventors: Masahiro Kiyotoshi, Kazuhiro Eguchi, Masaaki Nakabayashi, Fumihiko Inoue
  • Publication number: 20020071239
    Abstract: The present invention relates to semiconductor techniques using high dielectric oxides, more specifically to a thin film forming method for forming a thin film which is suitable as the electrodes of the oxide high dielectrics, a capacitor device using the oxide high dielectrics and a method for fabricating the same, an a semiconductor device using the capacitor device and a method for fabricating the semiconductor device. The capacitor device comprises at least one of a pair of electrodes which is formed of a material containing titanium nitride of (200) orientation. This permits the capacitor device to have good quality even in a case that the capacitor dielectric film is formed of a high dielectric thin film grown in an oxidizing atmosphere. The capacitor device includes the electrodes of titanium nitride film, whereby the electrodes can be patterned by RIE, which much improves processing precision of the electrode patterning, and throughputs.
    Type: Application
    Filed: October 2, 1998
    Publication date: June 13, 2002
    Inventors: MASAAKI NAKABAYASHI, TETSURO TAMURA, HIDEYUKI NOSHIRO
  • Publication number: 20020027303
    Abstract: A method of manufacturing an optical element is disclosed which comprises the steps of providing a molding material onto a mold; giving a local temperature difference to an interface between the mold and the molding material to separate the mold and the molding material from each other in an area; and successively enlarging the area of separation made by the temperature difference to entirely separate the mold and the molding material from each other.
    Type: Application
    Filed: August 14, 2001
    Publication date: March 7, 2002
    Inventor: Masaaki Nakabayashi
  • Publication number: 20020024734
    Abstract: The present invention provides a diffraction optical element comprising a first optical member having a first diffraction grating, a second optical member having a second diffraction grating, wherein the first and second optical members are stacked so that the first and second diffraction gratings faces to each other inside the stacked members and so that a space is formed between the diffraction gratings, and a sealing member for hermetically sealing the space between the diffraction gratings.
    Type: Application
    Filed: August 27, 2001
    Publication date: February 28, 2002
    Inventor: Masaaki Nakabayashi
  • Publication number: 20020015222
    Abstract: A diffraction optical element comprises a substrate, a diffraction grating formed on the substrate with a material with low ultraviolet resistance and an ultraviolet screening means arranged on the substrate at a position closer to the incident light receiving side of the optical element relative to the diffraction grating. The ultraviolet screening means comprises a dielectric multilayer film and is formed on the other side of the substrate than the side carrying the diffraction grating. Alternatively, the ultraviolet screening means may be provided as a separate member from a diffraction optical element and arranged at a position closer to the incident light receiving side of the diffraction optical element in an optical system.
    Type: Application
    Filed: March 14, 2001
    Publication date: February 7, 2002
    Inventors: Tetsuo Kuwabara, Masaaki Nakabayashi
  • Patent number: 6337238
    Abstract: A semiconductor memory device includes a memory cell capacitor for storing information, wherein the memory cell capacitor includes a capacitor insulation film of a double oxide on a lower electrode. The lower electrode has a layered structure of Ir/IrO2/Ir or Ru/RuO2/Ru acting as a diffusion barrier of oxygen or Pb. Further, the use of a Pt—Ir alloy is disclosed for the lower electrode.
    Type: Grant
    Filed: February 24, 1999
    Date of Patent: January 8, 2002
    Assignee: Fujitsu Limited
    Inventor: Masaaki Nakabayashi
  • Publication number: 20010026399
    Abstract: A diffractive optical element having plural diffraction grating surfaces accumulated, wherein a pair of diffraction grating surfaces are positioned so that a protrusion and/or a recess formed on an outside of one diffraction grating surface engages with a recess and/or a protrusion formed on an outside of the other diffraction grating surface, and wherein the pair of diffraction grating surfaces are defined on materials having different refractive indices and different dispersions and being formed into a kinoform, or a shape and a height of blazed or binary, close to it, such that a largest optical path difference to be applied to light rays passing through the diffraction grating surfaces with respect to plural wavelengths becomes equal to a multiple, by an integral number, of the wavelength.
    Type: Application
    Filed: September 23, 1999
    Publication date: October 4, 2001
    Inventors: MASAAKI NAKABAYASHI, JUNJI TERADA, SENICHI HAYASHI
  • Publication number: 20010024849
    Abstract: A high-dielectric capacitor is formed by using a Ru lower electrode having a (002)-oriented principal surface, by depositing thereon a Ta2O5 film such that the Ta2O5 film has a (100)-principal surface.
    Type: Application
    Filed: April 26, 2001
    Publication date: September 27, 2001
    Applicant: FUJITSU LIMITED
    Inventors: Jun Lin, Masaaki Nakabayashi
  • Patent number: 6271077
    Abstract: The present invention relates to semiconductor techniques using high dielectric oxides, more specifically to a thin film forming method for forming a thin film which is suitable as the electrodes of the oxide high dielectrics, a capacitor device using the oxide high dielectrics and a method for fabricating the same, an a semiconductor device using the capacitor device and a method for fabricating the semiconductor device. The capacitor device comprises at least one of a pair of electrodes which is formed of a material containing titanium nitride of (200) orientation. This permits the capacitor device to have good quality even in a case that the capacitor dielectric film is formed of a high dielectric thin film grown in an oxidizing atmosphere. The capacitor device includes the electrodes of titanium nitride film, whereby the electrodes can be patterned by RIE, which much improves processing precision of the electrode patterning, and throughputs.
    Type: Grant
    Filed: November 4, 1999
    Date of Patent: August 7, 2001
    Assignee: Fujitsu Limited
    Inventors: Masaaki Nakabayashi, Tetsuro Tamura, Hideyuki Noshiro
  • Patent number: 6249040
    Abstract: A high-dielectric capacitor is formed by using a Ru lower electrode having a (002)-oriented principal surface, by depositing thereon a Ta2O5 film such that the Ta2O5 film has a (100)-principal surface.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: June 19, 2001
    Assignee: Fujitsu Limited
    Inventors: Jun Lin, Masaaki Nakabayashi
  • Patent number: 6025222
    Abstract: A method for growing a dielectric film containing Sr on a substrate includes the steps of: dissolving a Sr compound containing Sr((CH.sub.3).sub.5 C.sub.5).sub.2 into an organic solvent or mixing Sr(thd).sub.2 and an amine compound to form a source material; vaporizing the source material to produce a gaseous source material; and decomposing the gaseous source material, obtained in the step of vaporization, in the vicinity of a surface of a substrate held in a reaction chamber, to cause a deposition of a dielectric film containing Sr upon the surface of the substrate.
    Type: Grant
    Filed: February 10, 1995
    Date of Patent: February 15, 2000
    Assignee: Fujitsu Limited
    Inventors: Takafumi Kimura, Hideaki Yamauchi, Masaaki Nakabayashi
  • Patent number: 5905278
    Abstract: A semiconductor memory device includes a memory cell capacitor for storing information, wherein the memory cell capacitor includes a capacitor insulation film of a double oxide on a lower electrode. The lower electrode has a layered structure of Ir/IrO.sub.2 /Ir or Ru/RuO.sub.2 /Ru acting as a diffusion barrier of oxygen or Pb. Further, the use of a Pt--Ir alloy is disclosed for the lower electrode.
    Type: Grant
    Filed: July 29, 1997
    Date of Patent: May 18, 1999
    Assignee: Fujitsu Limited
    Inventor: Masaaki Nakabayashi
  • Patent number: 5874364
    Abstract: The present invention relates to semiconductor techniques using high dielectric oxides, more specifically to a thin film forming method for forming a thin film which is suitable as the electrodes of the oxide high dielectrics, a capacitor device using the oxide high dielectrics and a method for fabricating the same, an a semiconductor device using the capacitor device and a method for fabricating the semiconductor device. The capacitor device comprises at least one of a pair of electrodes which is formed of a material containing titanium nitride of (200) orientation. This permits the capacitor device to have good quality even in a case that the capacitor dielectric film is formed of a high dielectric thin film grown in an oxidizing atmosphere. The capacitor device includes the electrodes of titanium nitride film, whereby the electrodes can be patterned by RIE, which much improves processing precision of the electrode patterning, and throughputs.
    Type: Grant
    Filed: March 26, 1996
    Date of Patent: February 23, 1999
    Assignee: Fujitsu Limited
    Inventors: Masaaki Nakabayashi, Tetsuro Tamura, Hideyuki Noshiro