Patents by Inventor Masaaki Onomura
Masaaki Onomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10771057Abstract: A semiconductor device of embodiments includes a first normally-off transistor having a first electrode, a second electrode, and a first control electrode, a normally-on transistor having a third electrode electrically connected to the second electrode via a first wiring, a fourth electrode, and a second control electrode, a second normally-off transistor having a fifth electrode, a sixth electrode electrically connected to the third electrode via a second wiring, and a third control electrode, a first diode having a first anode electrically connected to the second control electrode and a first cathode electrically connected to the third electrode, and a capacitor having a first end portion connected to the first anode and the second control electrode and a second end portion.Type: GrantFiled: January 17, 2020Date of Patent: September 8, 2020Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Akira Yoshioka, Toru Sugiyama, Masaaki Iwai, Naonori Hosokawa, Masaaki Onomura, Hung Hung, Yasuhiro Isobe
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Publication number: 20190271083Abstract: According to one embodiment, a film formation apparatus includes a substrate support member, a first gas supplier disposed above the substrate support member and supplying a first gas, a second gas supplier disposed between the substrate support member and the first gas supplier and supplying a second gas, and a plate member disposed between the first gas supplier and the second gas supplier and having a hole, the plate member defining a plasma generation area between the first gas supplier and the plate member, the plasma generation area generating plasma of the first gas, wherein the hole has a diameter between 0.1 to 2 mm and a depth between 0.1 to 5 mm.Type: ApplicationFiled: September 7, 2018Publication date: September 5, 2019Applicant: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Yasuhiro ISOBE, Naoharu SUGIYAMA, Takayuki SAKAI, Masaaki ONOMURA
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Patent number: 8796111Abstract: According to one embodiment, stacked layers of a nitride semiconductor include a substrate, a single crystal layer and a nitride semiconductor layer. The substrate does not include a nitride semiconductor and has a protrusion on a major surface. The single crystal layer is provided directly on the major surface of the substrate to cover the protrusion, and includes a crack therein. The nitride semiconductor layer is provided on the single crystal layer.Type: GrantFiled: July 19, 2013Date of Patent: August 5, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hideto Sugawara, Masaaki Onomura
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Publication number: 20130302931Abstract: According to one embodiment, stacked layers of a nitride semiconductor include a substrate, a single crystal layer and a nitride semiconductor layer. The substrate does not include a nitride semiconductor and has a protrusion on a major surface. The single crystal layer is provided directly on the major surface of the substrate to cover the protrusion, and includes a crack therein. The nitride semiconductor layer is provided on the single crystal layer.Type: ApplicationFiled: July 19, 2013Publication date: November 14, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hideto Sugawara, Masaaki Onomura
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Patent number: 8502350Abstract: According to one embodiment, stacked layers of a nitride semiconductor include a substrate, a single crystal layer and a nitride semiconductor layer. The substrate does not include a nitride semiconductor and has a protrusion on a major surface. The single crystal layer is provided directly on the major surface of the substrate to cover the protrusion, and includes a crack therein. The nitride semiconductor layer is provided on the single crystal layer.Type: GrantFiled: May 6, 2011Date of Patent: August 6, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Hideto Sugawara, Masaaki Onomura
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Publication number: 20120153439Abstract: According to one embodiment, stacked layers of a nitride semiconductor include a substrate, a single crystal layer and a nitride semiconductor layer. The substrate does not include a nitride semiconductor and has a protrusion on a major surface. The single crystal layer is provided directly on the major surface of the substrate to cover the protrusion, and includes a crack therein. The nitride semiconductor layer is provided on the single crystal layer.Type: ApplicationFiled: May 6, 2011Publication date: June 21, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hideto Sugawara, Masaaki Onomura
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Publication number: 20110067625Abstract: A crystal growth method for forming a semiconductor film, the method includes: while revolving one or more substrates about a rotation axis, passing raw material gas and carrier gas from the rotation axis side in a direction substantially parallel to a major surface of the substrate. The center of the substrate is located on a side nearer to the rotation axis than a position at which growth rate of the semiconductor film formed by thermal decomposition of the raw material gas is maximized.Type: ApplicationFiled: November 29, 2010Publication date: March 24, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masaaki Onomura, Yoshiyuki Harada
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Patent number: 7862657Abstract: A crystal growth method for forming a semiconductor film, the method includes: while revolving one or more substrates about a rotation axis, passing raw material gas and carrier gas from the rotation axis side in a direction substantially parallel to a major surface of the substrate. The center of the substrate is located on a side nearer to the rotation axis than a position at which growth rate of the semiconductor film formed by thermal decomposition of the raw material gas is maximized.Type: GrantFiled: July 24, 2007Date of Patent: January 4, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masaaki Onomura, Yoshiyuki Harada
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Patent number: 7737467Abstract: A nitride semiconductor device comprises: a laminated body; a first and second main electrode provided in a second and third region, respectively, adjacent to either end of the first region on the major surface of the laminated body; and a third main electrode. The laminated body includes a first semiconductor layer of a nitride semiconductor and a second semiconductor layer of a nondoped or n-type nitride semiconductor having a wider bandgap than the first semiconductor layer, the second semiconductor layer being provided on the first semiconductor layer. The third main electrode is provided on the major surface of the laminated body and opposite to the control electrode across the second main electrode.Type: GrantFiled: August 22, 2006Date of Patent: June 15, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Masaaki Onomura
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Patent number: 7602829Abstract: According to an aspect of the embodiment, there is provided a semiconductor light emitting device including: a gallium nitride substrate; a multilayer film of nitride semiconductors provided on the gallium nitride substrate; a first film including a first silicon nitride layer; and a second film including a second silicon nitride layer and a laminated film provided on the second silicon nitride layer. The gallium nitride substrate and the multilayer film have a laser light emitting facet and a laser light reflecting facet. The first silicon nitride layer is provided on the laser light emitting facet. The multilayer film includes a light emitting layer, and the multilayer film has a laser light emitting facet and a laser light reflecting facet. The second silicon nitride layer is provided on the laser light reflecting facet, and the laminated film includes oxide layer and silicon nitride layer which are alternately laminated.Type: GrantFiled: October 11, 2006Date of Patent: October 13, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Matsuyama, Masaaki Onomura
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Patent number: 7554127Abstract: Disclosed is a semiconductor light-emitting element, comprising an n-type cladding layer; a light guide layer positioned on the n-type cladding layer; a multiple quantum well structure active layer positioned on the light guide layer; a p-type carrier overflow prevention layer positioned on the active layer and having an impurity concentration of 5×1018 cm?3 to not more than 3×1019 cm?3; a p-type light guide layer positioned on the p-type carrier overflow prevention layer and having an impurity concentration of 1×1018 cm?3 or more and less than that of the p-type carrier overflow prevention layer; and a p-type cladding layer positioned on the p-type light guide layer and having a band gap narrower than the p-type carrier overflow prevention layer, and a method of manufacturing the same.Type: GrantFiled: August 13, 2004Date of Patent: June 30, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Akira Tanaka, Masaaki Onomura
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Patent number: 7531397Abstract: A semiconductor substrate encompasses a GaN substrate and a single-crystal layer formed of III-V nitride compound semiconductor epitaxially grown on the GaN substrate. The GaN substrate has a surface orientation defined by an absolute value of an off-angle of the surface from {0001} plane towards <1-100> direction lying in a range of 0.12 degree to 0.35 degree and by an absolute value of an off-angle of the surface from {0001} plane towards <11-20> direction lying in a range of 0.00 degree to 0.06 degree.Type: GrantFiled: January 3, 2008Date of Patent: May 12, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Tachibana, Chie Hongo, Shinya Nunoue, Masaaki Onomura
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Patent number: 7498618Abstract: A nitride semiconductor device comprises: a substrate body including a conductive substrate portion and a high resistance portion; a first semiconductor layer of a nitride semiconductor provided on the substrate body; a second semiconductor layer provided on the first semiconductor layer; a first main electrode provided on the second semiconductor layer; a second main electrode provided on the second semiconductor layer; and a control electrode provided on the second semiconductor layer between the first main electrode and the second main electrode. The second semiconductor layer is made of a nondoped or n-type nitride semiconductor having a wider bandgap than the first semiconductor layer. The first main electrode is provided above the conductive portion and the second main electrode is provided above the high resistance portion.Type: GrantFiled: August 22, 2006Date of Patent: March 3, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Masaaki Onomura, Akira Tanaka, Koichi Tachibana, Masahiko Kuraguchi, Takao Noda, Tomohiro Nitta, Akira Yoshioka
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Publication number: 20080181275Abstract: According to an aspect of the embodiment, there is provided a semiconductor light emitting device including: a gallium nitride substrate; a multilayer film of nitride semiconductors provided on the gallium nitride substrate; a first film including a first silicon nitride layer; and a second film including a second silicon nitride layer and a laminated film provided on the second silicon nitride layer. The gallium nitride substrate and the multilayer film have a laser light emitting facet and a laser light reflecting facet. The first silicon nitride layer is provided on the laser light emitting facet. The multilayer film includes a light emitting layer, and the multilayer film has a laser light emitting facet and a laser light reflecting facet. The second silicon nitride layer is provided on the laser light reflecting facet, and the laminated film includes oxide layer and silicon nitride layer which are alternately laminated.Type: ApplicationFiled: October 11, 2006Publication date: July 31, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Takayuki Matsuyama, Masaaki Onomura
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Publication number: 20080113497Abstract: A semiconductor substrate encompasses a GaN substrate and a single-crystal layer formed of III-V nitride compound semiconductor epitaxially grown on the GaN substrate. The GaN substrate has a surface orientation defined by an absolute value of an off-angle of the surface from {0001} plane towards <1-100> direction lying in a range of 0.12 degree to 0.35 degree and by an absolute value of an off-angle of the surface from {0001} plane towards <11-20> direction lying in a range of 0.00 degree to 0.06 degree.Type: ApplicationFiled: January 3, 2008Publication date: May 15, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Koichi TACHIBANA, Chie Hongo, Shinya Nunoue, Masaaki Onomura
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Patent number: 7369592Abstract: A semiconductor laser device comprises: an active layer; a cladding layer of a first conductivity type; an insulating film; a first electrode; and a pad electrode provided on the first electrode. The cladding layer is provided above the active layer, and has a ridge portion constituting a striped waveguide and non-ridge portions adjacent to both sides of the ridge portion. The insulating film is covering side faces of the ridge portion and an upper face of the non-ridge portions. The first electrode has a gap portion provided above the non-ridge portions. The pad electrode is provided on the first electrode.Type: GrantFiled: March 14, 2006Date of Patent: May 6, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Akira Tanaka, Masaaki Onomura
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Patent number: 7358156Abstract: A method of manufacturing a compound semiconductor device comprises forming a scribed groove extending from an edge of a major surface of a laminated body to an internal region on the first major surface. The laminated body has the first major surface and a second major surface and is formed by crystal growth of a compound semiconductor multilayer film on a substrate. The scribed groove is shallow at the edge and deep in the internal region. The method may further comprise separating the laminated body into first and second portions separated by a separation plane including the scribed groove by applying load to the second major surface of the laminated body.Type: GrantFiled: March 16, 2006Date of Patent: April 15, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Akira Tanaka, Masaaki Onomura, Seiji Iida, Takayuki Matsuyama
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Patent number: 7339255Abstract: A semiconductor substrate encompasses a GaN substrate and a single-crystal layer formed of III-V nitride compound semiconductor epitaxially grown on the GaN substrate. The GaN substrate has a surface orientation defined by an absolute value of an off-angle of the surface from {0001} plane towards <1?100> direction lying in a range of 0.12 degree to 0.35 degree and by an absolute value of an off-angle of the surface from {0001} plane towards <11?20> direction lying in a range of 0.00 degree to 0.06 degree.Type: GrantFiled: July 21, 2005Date of Patent: March 4, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Tachibana, Chie Hongo, Shinya Nunoue, Masaaki Onomura
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Patent number: 7333523Abstract: A semiconductor laser device comprising: a first cladding layer of a first conductivity type; an active layer provided on the first cladding layer and having a quantum well structure; an overflow blocking layer of a second conductivity type provided on the overflow blocking layer. The active layer includes a region having an impurity concentration is 3×1017 cm?3 or more and having a thickness of 30 nm or less between the overflow blocking layer and a well layer in the active layer closet to the overflow blocking layer.Type: GrantFiled: July 11, 2006Date of Patent: February 19, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Akira Tanaka, Hideto Sugawara, Chie Hongo, Yoshiyuki Harada, Masaaki Onomura
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Publication number: 20080017099Abstract: A crystal growth method for forming a semiconductor film, the method includes: while revolving one or more substrates about a rotation axis, passing raw material gas and carrier gas from the rotation axis side in a direction substantially parallel to a major surface of the substrate. The center of the substrate is located on a side nearer to the rotation axis than a position at which growth rate of the semiconductor film formed by thermal decomposition of the raw material gas is maximized.Type: ApplicationFiled: July 24, 2007Publication date: January 24, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masaaki Onomura, Yoshiyuki Harada