Abstract: An object of the invention is to transmit a waveform suitable for the reception of signals, while suppressing an increase in man-hours needed for design. A transmission-reception device (2) includes: an antenna element (21) which is terminated at a virtual ground point side of the antenna element by a terminating element (213); a conductor plane (23) which has a predetermined potential and surrounds the antenna element (21); and a transmission circuit (25) that outputs a differential signal to both ends of the antenna element (21). An interval between the conductor plane (23) and a first outer edge (214) of the antenna element (21) is shorter than an interval between the conductor plane (23) and a second outer edge (215) of the antenna element (21).

Abstract: An object of the invention is to transmit a waveform suitable for the reception of signals, while suppressing an increase in man-hours needed for design. A transmission-reception device (2) includes: an antenna element (21) which is terminated at a virtual ground point side of the antenna element by a terminating element (213); a conductor plane (23) which has a predetermined potential and surrounds the antenna element (21); and a transmission circuit (25) that outputs a differential signal to both ends of the antenna element (21). An interval between the conductor plane (23) and a first outer edge (214) of the antenna element (21) is shorter than an interval between the conductor plane (23) and a second outer edge (215) of the antenna element (21).

Abstract: Provided is a noise analysis model and a noise analysis method that can analyze effects of substrate noise on each of elements included in a circuit to be analyzed. The noise analysis model includes first to third resistors. The first resistor serves as a substrate resistor in a semiconductor substrate between a first point set in the semiconductor substrate between a noise source and a transistor to which substrate noise from the noise source propagates through the semiconductor substrate and a second point set in the semiconductor substrate just below a back gate of the transistor. The second resistor serves as a substrate resistor in the semiconductor substrate between the second point and a fixed potential region near the transistor. The third resistor serves as a line resistor of a line connecting the fixed potential region and a power pad that supplies a ground potential.

Abstract: Provided is a noise analysis model and a noise analysis method that can analyze effects of substrate noise on each of elements included in a circuit to be analyzed. The noise analysis model includes first to third resistors. The first resistor serves as a substrate resistor in a semiconductor substrate between a first point set in the semiconductor substrate between a noise source and a transistor to which substrate noise from the noise source propagates through the semiconductor substrate and a second point set in the semiconductor substrate just below a back gate of the transistor. The second resistor serves as a substrate resistor in the semiconductor substrate between the second point and a fixed potential region near the transistor. The third resistor serves as a line resistor of a line connecting the fixed potential region and a power pad that supplies a ground potential.

Abstract: An active inductance circuit comprising a signal terminal (OUT) and having voltage and current characteristics, as viewed from this terminal, which are identical to those of a circuit comprising an inductance, this active inductance circuit having a structure in which the drain terminal of a first MOS transistor M1 and the gate terminal of a second MOS transistor M2 different in conductivity type from the first MOS transistor are connected to the signal terminal, the gate terminal of the first MOS transistor is connected to the source terminal of the second MOS transistor, a capacitor and a current source are connected to the source terminal of the second transistor, the source terminal of the first MOS transistor and the drain terminal of the second MOS transistor are connected to a power source and other terminals of the capacitor and current source are connected to another power source.

Abstract: A variable impedance circuit has an impedance block including a plurality of MOS transistors connected in parallel by switching and having impedances in accordance with powers of 2, the powers corresponding to the sequential orders of the MOS transistors arranged. A control unit controls ON or OFF of each of the MOS transistors to thereby select one of overall impedances of the MOS transistors. The step difference in the variable impedances is substantially a constant irrespective of the overall impedance selected.

Abstract: An active inductance circuit comprising a signal terminal (OUT) and having voltage and current characteristics, as viewed from this terminal, which are identical to those of a circuit comprising an inductance, this active inductance circuit having a structure in which the drain terminal of a first MOS transistor M1 and the gate terminal of a second MOS transistor M2 different in conductivity type from the first MOS transistor are connected to the signal terminal, the gate terminal of the first MOS transistor is connected to the source terminal of the second MOS transistor, a capacitor and a current source are connected to the source terminal of the second transistor, the source terminal of the first MOS transistor and the drain terminal of the second MOS transistor are connected to a power source and other terminals of the capacitor and current source are connected to another power source.

Abstract: A clock identification and reproduction circuit which synchronizes a clock signal with an input signal includes a voltage controlled generator for generating a clock signal, a phase comparator for detecting a phase difference between an input signal and a clock signal to generate a phase difference signal according to the phase difference, and a filter for synchronizing a clock signal of the voltage controlled generator in response to a phase difference signal, in which the phase comparator generates a phase difference signal when a specific pulse waveform of a pulse of an input signal changes.

Abstract: A semiconductor device includes first and second output stage transistors, and a first transistor, and a first constant current source, and a first specific transistor, and a second transistor, and a second constant current source and a second specific transistor. The first and second output stage transistors generate an output signal as a result of a push-pull operation, which are mutually connected in series between a first power supply and a second power supply. The first transistor has a control electrode, to which a first input signal is inputted, and is connected between the first power supply and the second power supply. The second transistor has a control electrode, to which a second input signal is inputted, and is connected between the first power supply and the second power supply.

Abstract: An apparatus for detecting an edge timing of an input signal and operating on the basis of the edge timing while power consumption thereof is reduced. The apparatus includes an edge detecting circuit that detects edges of an input signal to generate an edge timing representing signal representative of edge timings of the edges, a signal processing circuit responsive to the edge timing representing signal. The edge detection circuit outputs an enable signal to enable the signal processing circuit to operate when the edge detection circuit finds one of the edges. The signal processing circuit executes a signal processing of the edge timing representing signal in response to the enable signal.

Abstract: To provide a high speed digital PLL circuit which is easily manufactured by IC process. The phase of data signal is locked with a first clock of which frequency is the half of the data signal. Further, a second clock of which phase is shifted by &pgr;/2 compared with the first clock is used for determining phase delay or phase advance of the data signal compared with the first clock. VCO outputs the first clock and the second clock. The phase comparator for inputting the data signal, the first and second clock, outputs a first data sampled at rise up of the first clock, a second data sampled at fall down of the first clock, a first indication signal indicating the phase delay, and a second indication signal indicating the phase advance. The filter for inputting the first and second indication signal outputs a control voltage for VCO.

Abstract: A clock signal producing apparatus is composed of a detecting circuit and a clock signal outputting circuit. The detecting circuit detects edge timings of an input signal at which the input signal is inverted. The edge timings are quantized to a predetermined number of states. A clock signal outputting circuit outputs an outputted clock signal. A phase of the outputted clock signal is adjusted based on the edge timings.

Abstract: A PLL comprising a VCO, a phase comparator, a frequency comparator and a filter realizes an enlarged pull-in frequency range and increased operating frequency. The VCO generates a first clock signal and a second clock signal whose frequency is the same as that of the first clock signal and whose phase is ahead of that of the first clock signal. An input data signal is inputted to the phase comparator and the frequency comparator. The first clock signal is supplied to the phase comparator and the frequency comparator, and the second clock signal is supplied to the frequency comparator. The phase comparator executes phase comparison between the first clock signal and the input data signal, and outputs the result of the phase comparison.

Abstract: A variable impedance circuit has an impedance block including a plurality of MOS transistors connected in parallel by switching and having impedances in accordance with powers of 2, the powers corresponding to the sequential orders of the MOS transistors arranged. A control unit controls ON or OFF of each of the MOS transistors to thereby select one of overall impedances of the MOS transistors. The step difference in the variable impedances is substantially a constant irrespective of the overall impedance selected.

Abstract: A VCO (voltage-controlled oscillator) that can realize stable oscillation operation over a broad frequency range with a low level of jitter. The VCO includes a plurality of basic cells having differential input/output, and a center frequency adjustment circuit. The plurality of basic cells are serially connected in a ring. Each basic cell includes a circuit constituted by two delay circuits and an adder circuit, the delay times of the two delay circuits being each independently determined by the center frequency adjustment circuit. The output amplitude of each of the basic cells is controlled to a fixed value. In the adder circuit, the output of one of the delay circuits is multiplied by an addition proportion coefficient, following which the outputs of both delay circuits are added. In this way, the delay time for each basic cell can be set over a broad range.

Abstract: An apparatus for detecting an edge timing of an input signal and operating on the basis of the edge timing while power consumption thereof is reduced. The apparatus includes an edge detecting circuit that detects edges of an input signal to generate an edge timing representing signal representative of edge timings of the edges, a signal processing circuit responsive to the edge timing representing signal. The edge detection circuit outputs an enable signal to enable the signal processing circuit to operate when the edge detection circuit finds one of the edges. The signal processing circuit executes a signal processing of the edge timing representing signal in response to the enable signal.

Abstract: A frame synchronous circuit enables a frame synchronization in relation to high speed SDH (Synchronous Digital Hierarchy) signal to be realized with simple constitution. A shift register which performs serial-parallel conversion of an STM-N (Synchronous Transport Module-N (=1, 2, 3, . . . )) signal by 1-byte unit, is in use by way of shift registers 4, and 7 with parallel configuration inputting data alternately in every 1-bit, thus enabling sufficient time for processing operation of the data to be secured. Appearance of A1-byte on two shift registers can be generated by way of two kinds of patterns of output positions which are shifted by one bit with each other caused by input order toward the shift register. Thereby, when the A1-byte detecting circuit 6 detects the A1-byte at an inappropriate output position, slowing the STM-N signal by 1 bit at the 1-bit delay circuit in order to reverse the input order such that the A1-byte is detected at the normal output position.

Abstract: A semiconductor device includes first and second output stage transistors, and a first transistor, and a first constant current source, and a first specific transistor, and a second transistor, and a second constant current source and a second specific transistor. The first and second output stage transistors generate an output signal as a result of a push-pull operation, which are mutually connected in series between a first power supply and a second power supply. The first transistor has a control electrode, to which a first input signal is inputted, and is connected between the first power supply and the second power supply. The first constant current source is connected in series to the first transistor between the first power supply and the second power supply. The first specific transistor is connected in series to the first transistor and the first constant current source between the first power supply and the second power supply and is connected as current mirror to the first output stage transistor.

Abstract: A VCO (voltage-controlled oscillator) that can realize stable oscillation operation over a broad frequency range with a low level of jitter. The VCO includes a plurality of basic cells having differential input/output, and a center frequency adjustment circuit. The plurality of basic cells are serially connected in a ring. Each basic cell includes a circuit constituted by two delay circuits and an adder circuit, the delay times of the two delay circuits being each independently determined by the center frequency adjustment circuit. The output amplitude of each of the basic cells is controlled to a fixed value. In the adder circuit, the output of one of the delay circuits is multiplied by an addition proportion coefficient, following which the outputs of both delay circuits are added. In this way, the delay time for each basic cell can be set over a broad range.

Abstract: A phase locked loop has a voltage comparator (41) which compares a control voltage Vf supplied from a filter (15) to a voltage controlled oscillator (16) with a reference voltage VR1 supplied with a reference voltage supplying terminal (42). The reference voltage VR1 is not lower than a maximum voltage of an insensitive range of a VCO controller (17). When the control voltage Vf is lower than the reference voltage VR1, the voltage comparator 41 produces a logic high level signal. A charge pump (43) annuls a discharge signal supplied from a phase comparator (13) in response to the logic high level signal sent from the voltage comparator (41). The phase comparator (13) compares an input signal with an output clock signal supplied from the voltage controlled oscillator (16) to produce the discharge signal.