Abstract: Besides a frequency-phase comparator for input and VCO signals, a filter for a frequency-phase difference signal, and a VCO controlled by a filter output signal to produce a phase locked VCO signal, a PLL circuit comprises a VCO controller for controlling an oscillation frequency range of the VCO when the input and the VCO signals are continuously in collapse of synchronism longer than a predetermined time interval, such as a pull-in time of the PLL circuit, with the collapse detected by the comparator. Preferably, the VCO comprises an inverter loop, each inverter delay controlled by the filter output signal and a loop length controlled by a VCO control signal.

Abstract: A PLL circuit includes a sampling pulse generator and a loop circuit using a sample and hold circuit as a phase detector. The sampling pulse generator generates a sampling pulse signal at each level transition of an NRZ input signal. The sample and hold circuit samples a clock signal and hold a voltage signal corresponding to a voltage of the clock signal according to the sampling pulse signal. A voltage-controlled oscillator included in the loop circuit generates the clock signal whose frequency is controlled based on tho voltage signal received from the sample and hold circuit through a loop filter. The voltage signal remains at an appropriate level even when the NRZ input signal remains at the same level for a relatively long time. The sampling pulse generator includes a delay circuit for delaying the NRZ input signal and an exclusive-OR circuit receiving the NRZ input signal and the delayed signal.

Abstract: A pair of input signals are connected to a first and second differential amplifier. The positive outputs of the differential amplifiers are connected to a first load and a first output terminal while the negative outputs are connected to a second load and a second output terminal. A constant current source is connected to each differential amplifier, and a control signal is connected to an input of a third differential amplifier and a third constant current source is connected to the third differential amplifier. Voltage to current conversion circuits convert voltage outputs of the third differential amplifier into current and input the resulted current to a reference current input terminal of the first and second constant current sources. Differential output signals are obtained from the first and second output terminals.

Abstract: A feedback differential amplifying circuit comprising three-terminal type amplifying elements, each having an input terminal and two output terminals, wherein a variable capacitance circuit enabling variation of capacitance of a peaking circuit to obtain optimum peaking is provided. In the variable capacitance circuit, the capacitance of the peaking circuit is controlled by the junction capacitance of a three-terminal type amplifying element.