Abstract: An information processing system includes a processor, a main storage, a buffer storage for holding a copy of a part of data of the main storage, an address translator for translating a logical address composed of a page address portion and an address portion within the page into a real address and a system controller and a buffer storage control unit. The buffer storage control unit includes a first detector and a second detector.

Abstract: Provided is an information processing apparatus in which at least two processing units each having a buffer memory are mutually connected to each other and to a main storage unit through a bus. All of the processing units having the buffer memories continuously monitor the state of the bus. When one of the processing units generates an information updating request in order to update the storage content of the main storage unit, the other processing units read a memory address from the bus. The memory address corresponds to the information to be updated, and is sent to the main storage unit through the bus together with the information updating request. The memory address is compared with memory addresses contained in the buffer memory of the other processing units. If there is a coincidence, information in the relevant memory address exists in its own buffer memory. Thereafter this information is invalidated.