Abstract: A solid state imaging device detects the period of energy variation of discharge type illumination, and sets a total exposure time to match the detected period. The total exposure time is divided into alternating valid and invalid exposure times by a division ratio to make the sum of the valid exposure times equal to an actual exposure time corresponding to an actual speed of an electronic shutter. Charges accumulated in a CMOS sensor during the valid exposure times are stored in a floating diffusion, whereas charges accumulated during the invalid exposure times are drained. At the end of the total exposure time, the charges stored during the valid exposure times are converted to an electrical signal which is output to a signal processing circuit. This device can correct variation of output signals which corresponds to the illumination energy variation when the shutter is operated for imaging under high luminance illumination.

Abstract: A micro vacuum gauge includes a substrate, a floating structure that is held above the substrate by a supporting structure extending from the substrate in a state where the floating structure is thermally isolated from the substrate, a heat generator that is arranged in the floating structure to generate heat, and a temperature sensor that is arranged in the floating structure to measure a difference in temperature between the substrate and the floating structure. A second member having a lower emissivity than a first member surrounding the heat generator and the temperature sensor is formed at least on a surface of the floating structure by being joined to the first member.

Abstract: Each of three light receiving sections has a P-type well having a P+-type layer and an N-type layer formed therein. The P+-type layer is diffused from substrate surface to depth d1. A PN junction forming portion of the N-type layer is diffused from depth d1 to depth d2 which is greater than depth d1 so as to form, with the P-type well, a PN junction of a photodiode at depth d2. Depths d1 as well as depths d2 of the three light receiving sections are different from each other. The N-type layer has a charge output portion which is diffused from the PN junction to the substrate surface, and which is coupled by circuit coupling to a MOS transistor for reading out charge. This allows each light receiving section to have spectral characteristics, thereby providing a solid state imaging element and a solid state imaging device without using color filters.

Abstract: Adjacent pixels in a pixel circuit of an imaging device use a primary capacitance, an amplifying transistor, a reset switch and a selection switch in common. Each pixel has a photodiode and a transfer switch having first and second gates provided on the photodiode side and the primary capacitance side, respectively. In a pixel downsampling read mode, the first and second gate voltages of each pixel to be discarded are brought to high level, and thereafter the first and second gate voltages of each pixel to be read are brought to high level, to transfer charge generated in the photodiode of the pixel to be read to the primary capacitance and the photodiode in each pixel to be discarded. This enables reduction of the potential of the primary capacitance, and hence reduction of the pixel sensitivity than using only the primary capacitance to store charge transferred from the transfer switch.

Abstract: In an imaging device having an all-pixel read mode for reading signals from all pixels and a pixel downsampling read mode for reading signals by appropriately discarding pixels, adjacent ones of pixels use a floating diffusion capacitance, an amplifying transistor, a reset switch and a selection switch in common. In the pixel downsampling read mode, not only a primary capacitance but also a photodiode in each pixel to be discarded are used as capacitances for storing signal charges transferred from transfer switches. This makes it possible to lower the gate voltage of the amplifying transistor as compared with the case of using only the primary capacitance as a capacitance for storing signal charges transferred from a transfer switch to reduce the sensitivity of the pixels, thereby reducing the occurrence of flicker.

Abstract: Adjacent pixels in a pixel circuit of an imaging device use a primary capacitance, an amplifying transistor, a reset switch and a selection switch in common. Each pixel has a photodiode and a transfer switch having first and second gates provided on the photodiode side and the primary capacitance side, respectively. In a pixel downsampling read mode, the first and second gate voltages of each pixel to be discarded are brought to high level, and thereafter the first and second gate voltages of each pixel to be read are brought to high level, to transfer charge generated in the photodiode of the pixel to be read to the primary capacitance and the photodiode in each pixel to be discarded. This enables reduction of the potential of the primary capacitance, and hence reduction of the pixel sensitivity than using only the primary capacitance to store charge transferred from the transfer switch.

Abstract: In an imaging device having an all-pixel read mode for reading signals from all pixels and a pixel downsampling read mode for reading signals by appropriately discarding pixels, adjacent ones of pixels use a floating diffusion capacitance, an amplifying transistor, a reset switch and a selection switch in common. In the pixel downsampling read mode, not only a primary capacitance but also a photodiode in each pixel to be discarded are used as capacitances for storing signal charges transferred from transfer switches. This makes it possible to lower the gate voltage of the amplifying transistor as compared with the case of using only the primary capacitance as a capacitance for storing signal charges transferred from a transfer switch to reduce the sensitivity of the pixels, thereby reducing the occurrence of flicker.

Abstract: A solid state imaging device detects the period of energy variation of discharge type illumination, and sets a total exposure time to match the detected period. The total exposure time is divided into alternating valid and invalid exposure times by a division ratio to make the sum of the valid exposure times equal to an actual exposure time corresponding to an actual speed of an electronic shutter. Charges accumulated in a CMOS sensor during the valid exposure times are stored in a floating diffusion, whereas charges accumulated during the invalid exposure times are drained. At the end of the total exposure time, the charges stored during the valid exposure times are converted to an electrical signal which is output to a signal processing circuit. This device can correct variation of output signals which corresponds to the illumination energy variation when the shutter is operated for imaging under high luminance illumination.

Abstract: Each of three light receiving sections has a P-type well having a P+-type layer and an N-type layer formed therein. The P+-type layer is diffused from substrate surface to depth d1. A PN junction forming portion of the N-type layer is diffused from depth d1 to depth d2 which is greater than depth d1 so as to form, with the P-type well, a PN junction of a photodiode at depth d2. Depths d1 as well as depths d2 of the three light receiving sections are different from each other. The N-type layer has a charge output portion which is diffused from the PN junction to the substrate surface, and which is coupled by circuit coupling to a MOS transistor for reading out charge. This allows each light receiving section to have spectral characteristics, thereby providing a solid state imaging element and a solid state imaging device without using color filters.

Abstract: A method of manufacturing an infrared image sensor in which an etching gas is introduced through etching holes into a semiconductor substrate to form a hollow portion. The etching gas is introduced only through an etching hole in a splicing pillar when etching is started. This method provides an etching configuration which has a largest depth right beneath the splicing pillar and which becomes shallower toward ends of the substrate, and therefore there is no need for forming deep etching stoppers.

Abstract: A thermal infrared-detector array has semiconductor-junction elements as detectors. It has high sensitivity and low noise and is fabricated in semiconductor-fabrication process. The semiconductor-junction elements are located in a monocrystalline silicon layer overlying a silicon-oxide layer on a monocrystalline silicon substrate. A signal-output circuit reading out signals from the detector elements includes transistors located on the monocrystalline silicon substrate.

Abstract: Infrared solid-state imaging elements include an infrared absorbing section formed as to correspond to each pixel aligned in a two-dimensional pattern for absorbing incident infrared radiation and converting the same into heat. A temperature detector section is formed as to correspond to each pixel on a semiconductor substrate and are arranged of a plurality of serially connected silicon pn junction diodes that are biased in a forward direction. A hollow section is formed on each region on which the temperature detector section is formed on the semiconductor substrate. Supporting mechanisms are arranged of materials exhibiting large thermal resistance and which support the temperature detector portion above the hollow section on the semiconductor substrate. A joint column thermally couples the infrared absorbing section and the temperature detector section.

Abstract: Present invention provides a method of manufacturing an infrared image sensor in which an etching gas is introduced through etching holes in a plurality of positions into a semiconductor substrate to form a hollow portion, the etching gas is introduced only through an etching hole in a splicing pillar when etching is started. This method makes it possible to obtain this provides an etching configuration which has a largest depth right beneath the splicing pillar and which becomes shallower toward ends of the substrate, and therefore there is no need for forming deep etching stoppers as in the prior art.

Abstract: A two-dimensional infrared focal plane array of temperature detecting units is provided with the temperature detecting units being arranged for every pixel in a two-dimensional arrangement on a semiconductor substrate. Each temperature detecting unit is formed integrally with readout circuitry. Each temperature detecting unit further has a temperature detecting portion which is supported by support legs made of a high thermal resistance material to reduce heat flow to the semiconductor substrate. Each temperature detecting unit also has a temperature detecting element with an infrared ray absorbing portion which is spliced by at least one splicing pillar with the temperature detecting element.

Abstract: A sensor element provided with a silicon substrate having a semiconductor circuit, a sensing-element portion formed on the silicon substrate and connected to the semiconductor circuit, and a cavity portion formed by removing a silicon substrate portion below the sensing-element portion, in which a removal resistance region having resistance against substrate removal is provided in the silicon substrate between the semiconductor circuit and the cavity portion.

Abstract: A focal plane array comprising two-dimensionally arranged photodetectors, charge transfer devices, transfer gates and a pixel row selection circuit, the focal plane array being operated in such a manner that the signal charges are read out from the photodetectors to vertical charge transfer device in one horizontal retrace period and the signal charges stored in the vertical charge transfer device are transferred to outside of a photodetector array region, wherein the pixel row selection circuit comprises a shift register and a switching transistor connected between the shift register and the transfer gates; and by combination of driving the shift resister and driving the switching transistor the horizontal line is selected so that a photodetector from which signal charge is to be read out is selected.

Abstract: A solid state image sensor of charge sweep architecture comprises photodetectors in two-dimension, vertical charge transfer elements and a horizontal charge transfer element. A driver circuit for the vertical charge transfer elements mounted in the solid state image sensor comprises a circuit for setting initial states of shift registers and a circulation loop line connecting an output of the shift register at the last stage to an input of the shift register at a first stage. Thus, a lower consumption power and high efficiency charge transfer are provided in the solid state image sensor.

Abstract: A solid-state imaging device includes a two-dimensional array of photodetectors, a TG scanner outputting a selection pulse for reading out signal charges stored in the photodetectors, an interlace circuit receiving the selection pulse from said TG scanner and converting the selection pulse to a field storage mode operation pulse or to a frame storage mode operation pulse, and an interlace switching circuit receiving the pulse from said interlace circuit and switching the array of photodetectors between the field storage mode and the frame storage mode. The switching between the frame storage mode and the field storage mode is controlled by an external control signal. Therefore, the solid-state imaging device can select an optimum interlace system according to background conditions and the brightness and size of objects imaged.

Abstract: An infrared image sensor includes a plurality of Schottky type infrared detecting elements (8) arranged in array formed on one main surface of a semiconductor substrate (1a) or in a vicinity of the one main surface to allow incident infrared rays from the other main surface of the semiconductor substrate (1a). In this infrared image sensor (1), a high concentration impurity layer (12) is provided between one main surface and the other main surface of the semiconductor substrate (1a), which layer being provided with an infrared ray transparent aperture for the corresponding predetermined unit of the grouped infrared detecting elements (8).

Abstract: An image sensor using a charge sweep device as a vertical transfer device (3) and comprising a plurality of pixels (10) each of which is formed of a single photo-electro transforming element (1) and a single transfer gate (4) for transferring a signal charge from the photo-electro transforming element into the charge sweep device (3), wherein the width of the transfer gate (4) is equal to or larger than that of the photo-electro transforming element in the direction of charge transfer in the charge sweep device (3).