Abstract: A method of driving a charge detection circuit of floating diffusion amplifier type including, a second conductivity type diffusion region produced on a first conductivity type semiconductor substrate or layer, a voltage barrier gate electrode adjacent the diffusion region, a CCD final gate electrode adjacent the voltage barrier production gate electrode, an MOS transistor for resetting the diffusion region incorporating the diffusion region as a source electrode, a source follower circuit for receiving the voltage of the diffusion region as an input signal. When the signal charges are transferred to the voltage well below the CCD final gate electrode, only the charges exceeding a voltage barrier below the voltage barrier gate electrode are output to the diffusion region.

Abstract: Vertical transfer portions are provided for the respective columns of photodetectors arranged in a matrix. A charge transfer direction of every other vertical transfer portions is opposite to that of the remaining vertical transfer portions. The charges transferred in the opposite directions are outputted in different horizontal transfer portions. The charges transferred by the two horizontal transfer portions are outputted therefrom and brought together in a united form so as to be continuously outputted.

Abstract: A semiconductor memory device such as a MOS dynamic RAM comprises transistor portions (2, 3 and 5) for writing and reading a signal and capacitor portions (1, 2, 6 and 9) by pn junction for storing a signal. The capacitor portions have preferably as large a capacitance as possible. For this purpose, a capacitor hole (7) is formed in a p type semiconductor substrate (6) and an n type semiconductor region (9) is provided along the capacitor hole (7) so that the pn junction area therebetween is increased and the capacitance is made large.

Abstract: Diffusion self-aligned MOS transistors are applied to a solid state image sensing device so as to form in a self-alignment manner control regions (80) in which reading of signal charges from photosignal detecting regions (70) formed on a semiconductor (1) to charge transfer regions (30) is controlled.

Abstract: A charge-coupled device comprises a p type silicon substrate (130), a plurality of n type impurity regions (121) of a high impurity concentration, a plurality of n type impurity regions (140) of a low impurity concentration, a silicon oxide film (150) for defining a channel region (10), a gate oxide film (110), a plurality of gate electrodes (21, 31, 41, 51, 22, 32, 42 and 52) and clock bus lines (70, 80, 90 and 100) for applying a clock signal to the respective gate electrodes. The n type impurity regions (121) and (140) are formed alternately in the channel region (10) along a direction perpendicular to the charge transfer direction, whereby the potential in the channel region (10) changes in the above described perpendicular direction. The change of the potential causes a strong electric field in the channel region (10) in the above described perpendicular direction, which serves to prevent carriers from freezing to an impurity level at a low temperature.

Abstract: A CSD type solid-state image sensor comprises an n-type semiconductor substrate (10), p-type impurity regions (20, 30, 40) formed thereon spaced apart from each other, a photodetector portion (21) formed on the p-type impurity region (20), a transfer gate selecting circuit (700) formed on the p-type impurity region (30) and a vertical charge transfer device driving circuit (800) formed on the p-type impurity region (40). The photodetector portion (21) comprises a photodetector (101), a transfer gate (7) and a vertical charge transfer device (8), and the transfer gate (7) and the vertical charge transfer device (8) have a common gate electrode (201). The potential in the p-type impurity region (20) is set to -V.sub.PW by a power supply (50), while the potential in the p-type impurity regions (30, 40) is set to -V.sub.SW (V.sub.PW <V.sub.SW) by a power supply (60).

Abstract: An output circuit of a charge coupled device comprises a transistor (4, 5, 6) having a floating diffusion (5) provided to receive a series of signal charges from a charge transfer section. Each signal charge is transferred to the floating diffusion in synchronism with a drive clock applied to the charge transfer section. The transistor has a gate electrode (4) connected to receive a reset clock (.phi.R') applied at an interval longer than the period of the drive clock.

Abstract: A semiconductor memory device such as a MOS dynamic RAM comprises transistor portions (2, 3 and 5) for writing and reading a signal and capacitor portions (1, 2, 6 and 9) by pn junction for storing a signal. The capacitor portions have preferably as large a capacitance as possible. For this purpose, a capacitor hole (7) is formed in a p type semiconductor substrate (6) and an n type semiconductor region (9) is provided along the capacitor hole (7) so that the pn junction area therebetween is increased and the capacitance is made large.

Abstract: Grooves 8a are formed on a main surface of a semiconductor substrate 8 and a vertical charge transfer element is formed on a side wall of each groove 8a. As a result, the areas occupied by the vertical charge transfer elements on the main surface of the semiconductor substrate 8 are substantially zero, whereby the areas occupied by Schottky barrier photo sensors 1 can be increased.

Abstract: A solid-state image sensor including pixels including photodetectors (111-148) for detecting light signals and charge sweep devices (210-240) for transferring signal charges. The pixels are arranged in first and second directions orthogonal to each other. A transfer gate scanning circuit (600) sequentially selects a pixel row from a plurality of pixel rows arranged in a second direction. A charge sweep device scanning circuit (700) supplies readout signals to the selected pixel rows so that signal charges may be read out, a plurality of times, within a horizontal scanning interval from the photodetectors (111-148).

Abstract: A solid state imaging device comprises a plurality of photodetectors (111 to 149) disposed two-dimensionally on a semiconductor substrate and a plurality of vertical charge transfer devices (411 to 431 and 511 to 528). Transfer gates (211 to 249) are provided in association with the respective photodetector (111 to 149) and the respective vertical charge transfer devices so as to be disposed therebetween. The transfer gates (211 to 249) are electrically connected for each group of three transfer gates in a horizontal direction, a driving signal being applied selectively to each group from a scanning circuit (300). Accordingly, by means of one of the groups of the transfer gates (211 to 249), to which a driving signal is selectively applied from the scanning circuit (300), a signal charge generated in the corresponding ones of the photodetectors (111 to 149) is transferred to the vertical charge transfer devices (411 to 431 and 511 to 528).

Abstract: A solid-state image sensor comprises photo sensors (110 to 114, 211 to 214 and 311 to 314), transfer gates (121 to 124, 221 to 224 and 321 to 324), vertical charge transferring elements (130, 230 and 330), interfacing portions (140, 240 and 340), horizontal CCD (500) and a clock signal source (800). Each of the vertical charge transferring elements (130, 230 and 330) has a plurality of gate electrodes under which the respective channels are formed, each with a potential barrier provided for separating the channel from the adjacent channel. A plurality of potential wells separated by said plurality of potential barriers are formed in the vertical charge transferring elements in response to clock signals applied from said clock signal source to said gate electrodes.

Abstract: A solid-state image sensor comprises photo sensors (111 to 114, 211 to 214 and 311 to 314), transfer gates (121 to 124, 221 to 224 and 321 to 324), a selecting circuit (800), vertical charge transferring elements (130, 230 and 330) and a driving circuit (900) for applying clock signals to the vertical charge transferring elements. When the vertical charge transferring elements receive signal charge from the photo sensors, the vertical charge transferring elements constitute respectively a continuous potential well, and then transfer of the signal charge in the vertical charge transferring elements is performed by controlling the clock signals applied to the vertical charge transferring elements so as to move a potential barrier successively toward the moving direction of the charge.

Abstract: A solid image-pickup device having a scanning mechanism for reading and outputting outputs from photo-detectors. The scanning mechanism includes at least one charge transferring unit in which a plurality of MOS gates are arranged side by side. A MOS gate control unit applies signals to the plurality of MOS gates so as to form potential wells below all the gates of the charge transferring unit at a first period, to inject a signal charge from a photo-detector in the potential well across a transfer gate beneath the MOS gates at a second period, and causes the potential wells to successively be removed in the direction of the charge transfer. As a result, the signal charges below the MOS gates of the charge transferring unit are moved during a third period.