Patents by Inventor Masaharu Kinoshita
Masaharu Kinoshita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160005969Abstract: Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced.Type: ApplicationFiled: September 17, 2015Publication date: January 7, 2016Inventors: Yoshitaka Sasago, Akio Shima, Satoru Hanzawa, Takashi Kobayashi, Masaharu Kinoshita, Norikatsu Takaura
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Patent number: 9177999Abstract: A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.Type: GrantFiled: October 5, 2014Date of Patent: November 3, 2015Assignee: Hitachi, Ltd.Inventors: Yoshitaka Sasago, Masaharu Kinoshita, Takahiro Morikawa, Akio Shima, Takashi Kobayashi
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Patent number: 9153774Abstract: When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film.Type: GrantFiled: December 6, 2010Date of Patent: October 6, 2015Assignee: Hitachi, Ltd.Inventors: Yoshitaka Sasago, Masaharu Kinoshita, Mitsuharu Tai, Akio Shima, Kenzo Kurotsuchi, Takashi Kobayashi
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Patent number: 9153775Abstract: Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced.Type: GrantFiled: August 26, 2014Date of Patent: October 6, 2015Assignee: Hitachi, Ltd.Inventors: Yoshitaka Sasago, Akio Shima, Satoru Hanzawa, Takashi Kobayashi, Masaharu Kinoshita, Norikatsu Takaura
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Patent number: 9099177Abstract: With the aim of providing a semiconductor memory device being suitable for miniaturization and allowing a contact resistance to lower, the wiring structure of a memory array (MA) is formed as follows. That is, word lines (2) and bit lines (3) are extended in parallel to each other, each of the word lines is bundled with another word line, each of the bit lines is bundled with another bit line, and two bit lines formed vertically over respective bundled two word lines are separated electrically. Such a configuration makes it possible to: form a larger contact at a bundling section (MLC) of wires; and lower a contact resistance in the memory array suitable for miniaturization.Type: GrantFiled: June 10, 2011Date of Patent: August 4, 2015Assignee: Hitachi, Ltd.Inventors: Yoshitaka Sasago, Masaharu Kinoshita, Akira Kotabe, Takashi Kobayashi
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Patent number: 9070621Abstract: In a nonvolatile semiconductor memory device, there is provided a technique which promotes microfabrication by reducing a thickness of the device as suppressing an OFF current of a polysilicon diode which is a selective element. A polysilicon layer to which an impurity is doped at low concentration and which becomes an electric-field relaxation layer of the polysilicon diode which is a selective element of a resistance variable memory is formed so as to be divided into two or more layers such as polysilicon layers. In this manner, it is suppressed to form the crystal grain boundaries thoroughly penetrating between an n-type polysilicon layer and a p-type polysilicon layer in the electric-field relaxation layer, and therefore, it is prevented to generate a leakage current flowing through the crystal grain boundaries in application of a reverse-bias voltage without increasing a height of the polysilicon diode.Type: GrantFiled: November 10, 2013Date of Patent: June 30, 2015Assignee: Hitachi, Ltd.Inventors: Yoshitaka Sasago, Masaharu Kinoshita, Mitsuharu Tai, Takashi Kobayashi
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Patent number: 9024284Abstract: A superlattice phase change memory capable of increasing a resistance in a low resistance state is provided. The phase change memory includes a first electrode, a second electrode provided on the first electrode, and a phase change memory layer having a superlattice structure between the first electrode and the second electrode, the superlattice structure including to repeatedly formed layers of Sb2Te3 and GeTe. The phase change memory layer having the superlattice structure includes a Sb2Te3 layer containing Zr in contact with the first electrode.Type: GrantFiled: November 27, 2013Date of Patent: May 5, 2015Assignee: Hitachi, Ltd.Inventors: Takasumi Oyanagi, Norikatsu Takaura, Mitsuharu Tai, Masaharu Kinoshita, Takahiro Morikawa, Kenichi Akita, Masahito Kitamura
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Publication number: 20150118804Abstract: A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.Type: ApplicationFiled: October 5, 2014Publication date: April 30, 2015Inventors: Yoshitaka SASAGO, Masaharu KINOSHITA, Takahiro MORIKAWA, Akio SHIMA, Takashi KOBAYASHI
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Publication number: 20140361241Abstract: Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced.Type: ApplicationFiled: August 26, 2014Publication date: December 11, 2014Inventors: Yoshitaka Sasago, Akio Shima, Satoru Hanzawa, Takashi Kobayashi, Masaharu Kinoshita, Norikatsu Takaura
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Patent number: 8866123Abstract: A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.Type: GrantFiled: November 22, 2010Date of Patent: October 21, 2014Assignee: Hitachi, Ltd.Inventors: Yoshitaka Sasago, Masaharu Kinoshita, Takahiro Morikawa, Akio Shima, Takashi Kobayashi
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Patent number: 8841646Abstract: Disclosed are a semiconductor storage device and a manufacturing method. The storage device has: a substrate; a first word line above the substrate; a first laminated body above the first word line and having N+1 first inter-gate insulating layers and N first semiconductor layers alternately laminated; a first bit line above the laminated body and extending in a direction that intersects the first word line; a first gate insulating layer on side surfaces of the first inter-gate insulating layers and the first semiconductor layers; a first channel layer on the side surface of the first gate insulating layer; and a first variable resistance material layer on the side surface of the first channel layer. The first variable resistance material layer is in a region where the first word line and the first bit line intersect. A polysilicon diode is used as a selection element.Type: GrantFiled: October 6, 2013Date of Patent: September 23, 2014Assignee: Hitachi, Ltd.Inventors: Yoshitaka Sasago, Akio Shima, Satoru Hanzawa, Takashi Kobayashi, Masaharu Kinoshita, Norikatsu Takaura
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Patent number: 8830740Abstract: The purpose of the present invention is to improve a rewriting transmission rate and reliability of a phase change memory. To attain the purpose, a plurality of phase change memory cells (SMC or USMC) which are provided in series between a word line (2) and a bit line (3) and have a selection element and a storage element that are parallel connected with each other are entirely set, and after that, a part of the cells corresponding to a data pattern is reset. Alternatively, the reverse of the operation is carried out.Type: GrantFiled: August 26, 2011Date of Patent: September 9, 2014Assignee: Hitachi, Ltd.Inventors: Yoshitaka Sasago, Hiroyuki Minemura, Takashi Kobayashi, Toshimichi Shintani, Satoru Hanzawa, Masaharu Kinoshita
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Publication number: 20140246646Abstract: A memory cell array having such a structure that can be realized with a simpler process and ideal for realizing a higher density is provided. Memory cells have a structure in which channel layers (88p and 89p) are formed on the side surfaces of each of a plurality of stacked structures which extends in the Y direction and is periodically formed in the X direction with a gate insulator film layer (9) interposed, and a resistance-change material layer (7) is formed so as to be electrically connected to two adjacent channel layers of the channel layers. Due to such a structure, it is not necessary to perform such a very difficult step that processes the resistance-change material and the silicons collectively and it is possible to provide the memory cell array with a simpler process.Type: ApplicationFiled: October 7, 2011Publication date: September 4, 2014Inventors: Yoshitaka Sasago, Masaharu Kinoshita
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Publication number: 20140232675Abstract: An input apparatus includes: a display unit (20) that displays a set value relating to a control item of a control apparatus (60, 80); a touch panel (30) that detects a touch operation; a processing unit (40) configured to modify the set value displayed on the display unit (20) according to the touch operation, and output a signal indicating the modified set value to the control apparatus (60, 80); and a measurement unit (40) that measures a time interval between the touch operation and a previous touch operation, wherein the processing unit (40) is configured to modify a variation amount by which the set value is varied such that the variation amount when the time interval is smaller than a threshold and the variation amount when the time interval equals or exceeds the threshold differ from each other.Type: ApplicationFiled: September 20, 2012Publication date: August 21, 2014Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Yasuhiko Yamamoto, Masaharu Kinoshita, Toshiyuki Tsutsumi
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Patent number: 8812190Abstract: A vehicular input manipulation apparatus has a target parameter switchover manipulating device and a setup changeover manipulating device in order to change setup contents of several control parameters for drive control of an in-vehicle apparatus. The target parameter switchover manipulating device executes switchover to designate one of the control parameters as a change target control parameter. The setup changeover manipulating device changes a setup content relative to the change target control parameter. When a control mode of the in-vehicle apparatus is changed into a predetermined control mode, a control circuit automatically enforces switchover relative to the change target control parameter by automatically replacing the control parameter, which has been designated as the change target control parameter, with an enforcement change target control parameter, which is a predetermined control parameter associated with the predetermined control mode.Type: GrantFiled: April 15, 2010Date of Patent: August 19, 2014Assignees: Denso Corporation, Toyota Shatai Kabushiki Kaisha, Toyota Jidosha Kabushiki KaishaInventors: Shinsuke Hisatsugu, Yasuhiko Yamazaki, Masaharu Kinoshita, Hiroaki Ichihara
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Publication number: 20140218999Abstract: With the aim of providing a semiconductor memory device being suitable for miniaturization and allowing a contact resistance to lower, the wiring structure of a memory array (MA) is formed as follows. That is, word lines (2) and bit lines (3) are extended in parallel to each other, each of the word lines is bundled with another word line, each of the bit lines is bundled with another bit line, and two bit lines formed vertically over respective bundled two word lines are separated electrically. Such a configuration makes it possible to: form a larger contact at a bundling section (MLC) of wires; and lower a contact resistance in the memory array suitable for miniaturization.Type: ApplicationFiled: June 10, 2011Publication date: August 7, 2014Inventors: Yoshitaka Sasago, Masaharu Kinoshita, Akira Kotabe, Takashi Kobayashi
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Patent number: 8783922Abstract: Disclosed is a display device capable of achieving a decorative effect by utilizing a color filter at the front of a light-emitting display unit. Also disclosed is a meter device using the display device. Specifically disclosed is a display device comprising a light-emitting display unit and a color filter, which is arranged at the front of the light-emitting display unit. A light-emitting element for decoration is provided on the outside of the light-emitting display unit. The color filter is provided with a light-discharging surface for discharging the light from the light-emitting element for a decorative appearance in the forward direction.Type: GrantFiled: November 30, 2009Date of Patent: July 22, 2014Assignees: Toyota Shatai Kabushiki Kaisha, Yazaki Corporation, Toyota Jidosha Kabushiki KaishaInventors: Hiroaki Ichihara, Masaharu Kinoshita, Yoshifumi Tatsuta, Takahiro Shimada, Koji Nomura, Masato Minakata, Koji Aikawa
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Patent number: 8772746Abstract: A semiconductor memory device in which the cell area can be decreased and the minimum feature size is not restricted by the thickness of the material forming the memory cell. In a semiconductor memory device, a gate insulating film, a channel extending in a direction X, and a resistance change element extending in the direction X are formed successively above multiple word lines extending in a direction Y, and a portion of the channel and a portion of the resistance change element are disposed above each of the plurality of the word lines. Such configuration can decrease the cell area and ensure the degree of design freedom.Type: GrantFiled: January 13, 2012Date of Patent: July 8, 2014Assignee: Hitachi, Ltd.Inventors: Masaharu Kinoshita, Yoshitaka Sasago, Takashi Kobayashi
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Publication number: 20140151622Abstract: A superlattice phase change memory capable of increasing a resistance in a low resistance state is provided. The phase change memory includes a first electrode, a second electrode provided on the first electrode, and a phase change memory layer having a superlattice structure between the first electrode and the second electrode, the superlattice structure including to repeatedly formed layers of Sb2Te3 and GeTe. The phase change memory layer having the superlattice structure includes a Sb2Te3 layer containing Zr in contact with the first electrode.Type: ApplicationFiled: November 27, 2013Publication date: June 5, 2014Inventors: Takasumi Oyanagi, Norikatsu Takaura, Mitsuharu Tai, Masaharu Kinoshita, Takahiro Morikawa, Kenichi Akita, Masahito Kitamura
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Publication number: 20140103287Abstract: Disclosed are a semiconductor storage device and a manufacturing method. The storage device has: a substrate; a first word line above the substrate; a first laminated body above the first word line and having N+1 first inter-gate insulating layers and N first semiconductor layers alternately laminated; a first bit line above the laminated body and extending in a direction that intersects the first word line; a first gate insulating layer on side surfaces of the first inter-gate insulating layers and the first semiconductor layers; a first channel layer on the side surface of the first gate insulating layer; and a first variable resistance material layer on the side surface of the first channel layer. The first variable resistance material layer is in a region where the first word line and the first bit line intersect. A polysilicon diode is used as a selection element.Type: ApplicationFiled: October 6, 2013Publication date: April 17, 2014Applicant: Hitachi, Ltd.Inventors: Yoshitaka Sasago, Akio Shima, Satoru Hanzawa, Takashi Kobayashi, Masaharu Kinoshita, Norikatsu Takaura