Abstract: A semiconductor substrate is of a first conductivity type and has a retrograde well impurity concentration. A first of the first conductivity type and having a second impurity concentration with an impurity concentration peak is formed on a main surface of the semiconductor substrate. A first impurity layer of a third impurity concentration comes into contact with the underside of the retrograde well. The third impurity concentration is smaller than the impurity concentration peak of the first impurity concentration and the second impurity concentration. An element is formed on the retrograde well.

Abstract: A semiconductor substrate is of a first conductivity type and has a first impurity concentration. A first impurity layer of the first conductivity type and having a second impurity concentration with an impurity concentration peak is formed on a main surface of the semiconductor substrate. A second impurity layer of a third impurity concentration comes into contact with the underside of the first impurity layer. The third impurity concentration is smaller than the impurity concentration peak of the first impurity concentration and the second impurity concentration. An element is formed on the first impurity layer.

Abstract: In a semiconductor substrate of a semiconductor device, a plural impurity layers of the same conductivity type as the substrate are formed. An impurity region of an opposite conductivity type penetrates at least one of the impurity layers to a certain depth from the main surface of the semiconductor substrate. The bottom surface of the impurity region terminates between the impurity layers where the impurity concentration is lower. A contact conductor is led out from the impurity region.

Abstract: An N type field effect transistor having a higher resistivity to hot carriers and exhibiting a higher current handling capability even when used at a low gate voltage, and a method of manufacturing such a transistor are provided. A nitrided oxide film is formed on a drain avalanche hot carrier injection region. The nitrided oxide film is highly resistive to drain avalanche hot carriers as compared to a silicon oxide film. The silicon oxide film is formed on a channel hot electron injection region. The silicon oxide film is highly resistive to channel hot electrons as compared to the nitrided oxide film. A major portion of a gate insulator film is a silicon oxide film. The silicon oxide film exhibits a higher current handling capability at a low gate voltage as compared to the nitrided oxide film.

Abstract: An N type field effect transistor having a higher resistivity to hot carriers and exhibiting a higher current handling capability even when used at a low gate voltage, and a method of manufacturing such a transistor are provided. A nitrided oxide film is formed on a drain avalanche hot carrier injection region. The nitrided oxide film is highly resistive to drain avalanche hot carriers as compared to a silicon oxide film. The silicon oxide film is formed on a channel hot electron injection region. The silicon oxide film is highly resistive to channel hot electrons as compared to the nitrided oxide film. A major portion of a gate insulator film is a silicon oxide film. The silicon oxide film exhibits a higher current handling capability at a low gate voltage as compared to the nitrided oxide film.

Abstract: A semiconductor device includes a p-type silicon substrate, a first well of p-type formed in a major surface of the silicon substrate, and a second well of n-type formed close to the first well in the major surface of the silicon substrate. A third well of p-type is formed inside the second well and, furthermore, a conductive layer including p-type impurities of higher concentration than that of the first well is formed as extending immediately below both the first well and the second well. In accordance with this structure, even if minority carriers are injected, they recombine and disappear in the conductive layer, so that the implantation of the carriers into the first well is prevented. As a result, various disadvantageous phenomena due to the injection of the minority carriers are prevented and a semiconductor device having a stable device characteristic and high integration density is provided.

Abstract: A semiconductor device includes a p-type silicon substrate, a first well of p-type formed in a major surface of the silicon substrate, and a second well of n-type formed close to the first well in the major surface of the silicon substrate. A third well of p-type is formed inside the second well and, furthermore, a conductive layer including p-type impurities of higher concentration than that of the first well is formed as extending immediately below both the first well and the second well. In accordance with this structure, even if minority carriers are injected, they recombine and disappear in the conductive layer, so that the implantation of the carriers into the first well is prevented. As a result, various disadvantageous phenomena due to the injection of the minority carriers are prevented and a semiconductor device having a stable device characteristic and high integration density is provided.

Abstract: An N type field effect transistor having a higher resistivity to hot carriers and exhibiting a higher current handling capability even when used at a low gate voltage, and a method of manufacturing such a transistor are provided. A nitrided oxide film is formed on a drain avalanche hot carrier injection region. The nitrided oxide film is highly resistive to drain avalanche hot carriers as compared to a silicon oxide film. The silicon oxide film is formed on a channel hot electron injection region. The silicon oxide film is highly resistive to channel hot electrons as compared to the nitrided oxide film. A major portion of a gate insulator film is a silicon oxide film. The silicon oxide film exhibits a higher current handling capability at a low gate voltage as compared to the nitrided oxide film.

Abstract: A semiconductor memory device comprises a p.sup.- -type semiconductor substrate (1), p.sup.+ -type regions (15, 80) formed thereon, n.sup.+ -type regions (6, 7) surrounded with the p.sup.+ -type regions (15, 80), a first gate electrode (2) formed on a charge storage region in the n.sup.+ -type region (6), and a second gate electrode (3) formed on the p.sup.+ -type region (80) and serving as a word line. The p.sup.+ -type regions (15, 80) prevent passage of electrons out of electron-hole pairs induced by alpha rays so as to prevent occurrence of soft errors. An oxide film (16) is formed on the side wall of the second gate electrode (3), a titanium silicide film (17) is formed on the n.sup.+ -type regions (6, 7) and a titanium silicide film (18) is formed on the second gate electrode (3) in a self-aligning manner. Therefore, increase of interconnection resistance of the second gate electrode (3 ) and diffusion resistance of the n.sup.+ -type regions (6, 7) is prevented.

Abstract: A semiconductor memory device having memory cells formed adjacent to each other comprises a P type semiconductor substrate having adjacent two trenches, a P.sup.+ impurity region formed in the side portions and the bottom portions of the trenches, n type first polysilicon layers serving as common electrodes formed in the upper portion of the P.sup.+ impurity region through an insulating film, second polysilicon layers formed inside and in the upper portion of the trenches formed of the first polysilicon layers through an insulating film, and a third polysilicon layer formed on the second polysilicon layers, only the third polysilicon layer constituting a connecting electrode between the adjacent memory cells.

Abstract: An MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) of the present invention comprises two source.multidot.drain impurity regions formed spaced apart from each other in a semiconductor substrate. At least a drain side of the two impurity regions has a so called LDD structure in which a region of higher concentration and a region of lower concentration are off set. A gate electrode having a rectangular cross section is formed on the semiconductor substrate between the source and drain with an insulating film interposed therebetween. The gate electrode fully covers the lower concentration region of the LDD structure directly therebelow. The position of the side surface of the gate electrode is approximately aligned with the end surface of the region of higher concentration. The impurity region of lower concentration of the LDD is formed by oblique ion implantation.

Abstract: A MOS FET comprises a pair of source and drain impurity regions, a gate oxide film and a gate electrode. The source and drain regions have an LDD structure in which high concentration impurity regions and low concentration impurity regions are set off. The gate electrode is formed to extend over the channel region and contains sidewalls overlying the low concentration impurity regions. In addition, portions of the gate oxide film located between the sidewalls of the gate electrode and the respective low concentration impurity regions are formed to have a film thickness larger than that of the portion located between the gate electrode and the channel region. The thick portion of the oxide film underlying the gate sidewalls form a charge storage layer which reduces the resistance of the low impurity concentration region while minimizing the gate capacitance. In another example, conductive sidewall spacers are formed on sidewalls of a gate electrode through an insulating film.

Abstract: A semiconductor memory device comprises a semiconductor substrate having a trench, first polysilicon serving as a charge storage region formed through an insulating film in an inner portion of the trench, and second polysilicon serving as a capacitor electrode formed through an insulating film inside of the first polysilicon. An impurity contact region connects the charge storage region to a transfer gate transistor in the surface adjacent the trench so that information charges are transferred. A method for manufacturing such a semiconductor memory device includes forming a trench in the major surface of the semiconductor substrate and forming a first insulating layer in an inner portion of the trench. On at least one sidewall of the trench, the first insulating layer begins at a distance below the upper end of the trench. The impurity contact region is formed by obliquely implanting ions in the region of the sidewall above the first insulating layer and in a portion of the major surface of the substrate.

Abstract: A static type semiconductor memory device includes memory cells each including a pair of field effect transistors (FETs) each having a gate electrode cross-coupled to a drain region connected to a power source terminal by way of a load register. The memory device includes a semiconductor substrate of a first conductivity type, polycrystal silicon layers containing impurities of a second conductivity type and first and second FETs. The polycrystal silicon layers are formed with a spacing from one another for defining a channel region on the substrate. The first and second FETs are formed on the substrate and each includes source and drain regions of a second conductivity type and a gate electrode. The source and drain regions are formed below the polycrystal silicon layers by introducing impurities from the polycrystal silicon layers into the substrate. The gate electrode is formed on the channel region and the polycrystal silicon layers with a gate insulating film interposed.

Abstract: In an MIS transistor of a type having LDD and salicide structures, the location of the boundary between the high and low impurity density source/drain regions and the positions of the salicide layers on the source/drain regions are independently controlled during fabrication using a double gate sidewall structure. An MIS transistor improved thereby has its boundary between the high and low impurity density source/drain regions at or displaced toward the control gate electrode with respect to the interface of the double gate sidewall structure.

Abstract: A static type semiconductor memory device includes memory cells each including a pair of field effect transistors (FETs) each having a gate electrode cross-coupled to a drain region connected to a power source terminal by way of a load register. The memory device includes a semiconductor substrate of a first conductivity type, polycrystal silicon layers containing impurities of a second conductivity type and first and second FETs. The polycrystal silicon layers are formed with a spacing from one another for defining a channel region on the substrate. The first and second FETs are formed on the substrate and each includes source and drain regions of a second conductivity type and a gate electrode. The source and drain regions are formed below the polycrystal silicon layers by introducing impurities from the polycrystal silicon layers into the substrate. The gate electrode is formed on the channel region and the polycrystal silicon layers with a gate insulating film interposed.

Abstract: A MOS FET comprises a pair of source and drain impurity regions, a gate oxide film and a gate electrode. The source and drain regions have an LDD structure in which high concentration impurity regions and low concentration impurity regions are set off. The gate electrode is formed to extend over the channel region and contains sidewalls overlying the low concentration impurity regions. In addition, portions of the gate oxide film located between the sidewalls of the gate electrode and the respective low concentration impurity regions are formed to have a film thickness larger than that of the portion located between the gate electrode and the channel region. The thick portion of the oxide film underlying the gate sidewalls form a charge storage layer which reduces the resistance of the low impurity concentration region while minimizing the gate capacitance. In another example, conductive sidewall spacers are formed on sidewalls of a gate electrode through an insulating film.

Abstract: In an MIS transistor of a type having LDD and salicide structures, the location of the boundary between the high and low impurity density source/drain regions and the positions of the salicide layers on the source/drain regions are independently controlled during fabrication using a double gate sidewall structure. An MIS transistor improved thereby has its boundary between the high and low impurity density source/drain regions at or displaced toward the control gate electrode with respect to the interface of the double gate sidewall structure.

Abstract: An MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) of the present invention comprises two source.multidot.drain impurity regions formed spaced apart from each other in a semiconductor substrate. At least a drain side of the two impurity regions has a so called LDD structure in which a region of higher concentration and a region of lower concentration are off set. A gate electrode having a rectangular cross section is formed on the semiconductor substrate between the source and drain with an insulating film interposed therebetween. The gate electrode fully covers the lower concentration region of the LDD structure directly therebelow. The position of the side surface of the gate electrode is approximately aligned with the end surface of the region of higher concentration. The impurity region of lower concentration of the LDD is formed by oblique ion implantation.

Abstract: A semiconductor memory device comprises a p.sup.- -type semiconductor substrate (1), thin p.sup.+ -type regions (15, 80) formed thereon, n.sup.+ -type regions (6, 7) surrounded with the p.sup.+ -type regions (15, 80), a first gate electrode (2) formed on a charge storage region in the n.sup.+ -type region (6), and a second gate electrode (3) formed on the p.sup.+ -type region (80) and serving as a word line. The p.sup.+ -type regions (15, 80) prevent passage of electrons out of electron-hole pairs induced by alpha rays so as to prevent occurrence of soft errors. Advantageously, the thin p+ layer used to control threshold voltage for a transfer gate of the device is extended and also used for prevention of such soft errors, thus providing reduced bulk for the device. In order to reduce bulk further, the n+-type regions (6, 7) are also reduced in thickness.