Patents by Inventor Masahide Inuishi

Masahide Inuishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4942448
    Abstract: A semiconductor apparatus having a region for isolation between devices comprises a semiconductor substrate, a polycrystalline silicon layer portions selectively formed to be spaced apart from each other on the semiconductor substrate, an impurity diffused region formed under the polycrystalline silicon layer, and a silicon oxide film for filling in a space between the respective adjacent portions of the polycrystalline silicon layer. The impurity diffused region constitutes a source or drain region of a field effect device such as a MOS transistor isolated by the silicon oxide film.
    Type: Grant
    Filed: October 25, 1988
    Date of Patent: July 17, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuhiro Tsukamoto, Masahide Inuishi, Masahiro Shimizu
  • Patent number: 4918500
    Abstract: A semiconductor memory device comprises a semiconductor substrate having a trench, first polysilicon serving as a charge storage region formed through an insulating film in an inner portion of the trench, and second polysilicon serving as a capacitor electrode formed through an insulating film inside of the first polysilicon, the charge storage regions being connected to a transfer gate in the upper end of the concave portion so that information charges are transferred.
    Type: Grant
    Filed: June 27, 1988
    Date of Patent: April 17, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Masahide Inuishi
  • Patent number: 4702797
    Abstract: A method of manufacturing a semiconductor device comprises the steps of forming memory cell portions (2, 4, 6, 11) on a p.sup.- -type semiconductor substrate (1), forming a gate insulator film (5) and a gate electrode (3) each having a larger width, by approximately 1 .mu.m, than the original width, ion-implanting p-type impurities utilizing the gate insulator film (5) and the gate electrode (3) as masks, to form p.sup.+ -type regions (120, 121), etching the side walls of the gate insulator film (5) and the gate electrode (3) to the original width and then, ion-implanting n-type impurities utilizing these regions as a mask, to form n.sup.+ -type regions (80, 81), and heat-treating these regions (80, 81, 120, 121), to form regions (80a, 81a, 120a, 121a). The p.sup.+ -type regions (120a, 121a) prevent passage of electrons out of electron-hole pairs induced by alpha rays, to prevent occurrence of soft errors. The p.sup.+ -type regions (120a, 121a) are located inside the n.sup.
    Type: Grant
    Filed: December 18, 1986
    Date of Patent: October 27, 1987
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroki Shimano, Masahiro Shimizu, Katsuhiro Tsukamoto, Masahide Inuishi