Patents by Inventor Masahide Okamoto

Masahide Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6118671
    Abstract: Ceramic circuit substrate which is sintered at 900 to 1,050.degree. C. and have low relative dielectric constant, thermal expansion coefficient comparable to that of silicon, and high bending strength, and a method of manufacturing are provided by using a glass with a softening point of 850 to 1,100.degree. C., that is, a glass having a composition included in an area in FIG. 1 (triangular composition diagram of SiO.sub.2 --B.sub.2 O.sub.3 --R.sub.2 O, a composition is represented by the position of a small circle, the number in a small circle represents the composition number) defined with lines connecting points representing the first, third, tenth, eleventh, and fourth compositions respectively as raw material.
    Type: Grant
    Filed: June 24, 1998
    Date of Patent: September 12, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Hirayoshi Tanei, Shoichi Iwanaga, Masahide Okamoto, Masato Nakamura, Kousaku Morita, Shousaku Ishihara, Fumikazu Tagami, Norio Sengoku, Tsuyoshi Fujita, Fumiyuki Kobayashi
  • Patent number: 5825632
    Abstract: Ceramic circuit substrate which is sintered at 900.degree. to 1,050.degree. C. and have low relative dielectric constant, thermal expansion coefficient comparable to that of silicon, and high bending strength, and a method of manufacturing are provided by using a glass with a softening point of 850.degree. to 1,100.degree. C., that is, a glass having a composition included in an area in FIG. 1 (triangular composition diagram of SiO.sub.2 --B.sub.2 O.sub.3 --R.sub.2 O, a composition is represented by the position of a small circle, the number in a small circle represents the composition number) defined with lines connecting points representing the first, third, tenth, eleventh, and fourth compositions respectively as raw material.
    Type: Grant
    Filed: August 8, 1995
    Date of Patent: October 20, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Hirayoshi Tanei, Shoichi Iwanaga, Masahide Okamoto, Masato Nakamura, Kousaku Morita, Shousaku Ishihara, Fumiyuki Kobayashi, Fumikazu Tagami, Norio Sengoku, Tsuyoshi Fujita
  • Patent number: 5731066
    Abstract: In an electronic circuit device having an input/output pin junction electrode, in order to remarkably improve the junction characteristics such as wettability and junction strength and to drastically simplify the production process, in forming an electronic circuit board in which glass ceramics is used for board material and a wiring conductor and junction electrode wherein the Cu is sized to extend beyond the pin hole so that solder only contacts it and not the ceramic circuit board. The wiring and junction electrode is formed in a same process while forming a cover coat on the electrode using board material, and Au or Au--Ni laminated film is formed on this electrode as occasion demands, and then an electronic component is connected thereto using a solder such a Au--Sn or Au--Ge.
    Type: Grant
    Filed: October 23, 1995
    Date of Patent: March 24, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Akihiro Ando, Osamu Yamada, Ryohei Satoh, Takashi Inoue, Masahide Okamoto, Fumiyuki Kobayashi, Toshihiko Ohta, Minoru Tanaka
  • Patent number: 5277723
    Abstract: A method of producing a sintered multi-layer ceramic body used for ceramic parts of various electronic devices such as multi-layer substrates for LSI packaging and highly functional structural materials and by applying a pressure and/or constraining force to an outermost surface of the laminate. The method is featured by the shape of the surfaces to which a pressure and/or constraining force are not applied, ranges of the pressure and/or the constraining force, and the like.
    Type: Grant
    Filed: September 19, 1991
    Date of Patent: January 11, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Hironori Kodama, Masahide Okamoto, Hideo Suzuki, Satoru Ogihara, Tadahiko Moyoshi, Fumiyuki Kobayashi
  • Patent number: 5097318
    Abstract: A cavity-down type package for a semiconductor device comprises an insulating base substrate on which the semiconductor device and another insulating cap substrate with plural outer connection terminals on its outer surface and with electrodes provided on conductive layers for electric conduction on its inner surface. The electrodes on the insulating base substrate and those on the insulating cap substrate are connected with each other by using conductive material such as bumps.
    Type: Grant
    Filed: April 3, 1989
    Date of Patent: March 17, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Akira Tanaka, Kazuji Yamada, Hirokazu Inoue, Hideo Arakawa, Masahide Okamoto